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<title>u-boot.git/arch/x86/cpu/intel_common/Makefile, branch v2018.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/cpu/intel_common/Makefile?h=v2018.09</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/x86/cpu/intel_common/Makefile?h=v2018.09'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2018-06-17T13:16:04Z</updated>
<entry>
<title>x86: Rename efi-x86 target to efi-x86_app</title>
<updated>2018-06-17T13:16:04Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2018-06-12T15:36:24Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3ebd892fda2d07f153a14cb30e60ae707e9e4208'/>
<id>urn:sha1:3ebd892fda2d07f153a14cb30e60ae707e9e4208</id>
<content type='text'>
To avoid confusion, let's rename the efi-x86 target to efi-x86_app.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>SPDX: Convert all of our single license tags to Linux Kernel style</title>
<updated>2018-05-07T13:34:12Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-05-06T21:58:06Z</published>
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<id>urn:sha1:83d290c56fab2d38cd1ab4c4cc7099559c1d5046</id>
<content type='text'>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>x86: Use X86_32BIT_INIT instead of X86_RESET_VECTOR</title>
<updated>2017-02-06T03:38:46Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-01-16T14:03:46Z</published>
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<id>urn:sha1:2eff989585518a2da60930fa603aad4d425bbe7d</id>
<content type='text'>
Use this new option to control the location of 32-bit init. This will allow
us to place this in SPL if needed.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add common SDRAM-init code</title>
<updated>2016-03-17T02:27:27Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-16T13:44:37Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=65dd1507e3b744954d43811a1e4d9f194d1bda64'/>
<id>urn:sha1:65dd1507e3b744954d43811a1e4d9f194d1bda64</id>
<content type='text'>
The code to call the memory reference code is common to several Intel CPUs.
Add common code for performing this init. Intel calls this 'Pre-EFI-Init'
(PEI), where EFI stands for Extensible Firmware Interface.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Move common PCH code into a common place</title>
<updated>2016-03-17T02:27:27Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-16T13:44:36Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7e4a6ae62c7ee567ae43e94445e561b3ec8343b9'/>
<id>urn:sha1:7e4a6ae62c7ee567ae43e94445e561b3ec8343b9</id>
<content type='text'>
The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Move Intel Management Engine code to a common place</title>
<updated>2016-03-17T02:27:24Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:07:00Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8b900a417527d9ad94dc4aab2c9d6717bdc50b33'/>
<id>urn:sha1:8b900a417527d9ad94dc4aab2c9d6717bdc50b33</id>
<content type='text'>
Some of the Intel ME code is common to several Intel CPUs. Move it into a
common location. Add a header file for report_platform.c also.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
[squashed in http://patchwork.ozlabs.org/patch/598372/]
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Move common CPU code to its own place</title>
<updated>2016-03-17T02:27:24Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:06:58Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=50dd3da0042b4502bab622ef7f72f628b842cf26'/>
<id>urn:sha1:50dd3da0042b4502bab622ef7f72f628b842cf26</id>
<content type='text'>
Some of the Intel CPU code is common to several Intel CPUs. Move it into a
common location along with required declarations.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Move common LPC code to its own place</title>
<updated>2016-03-17T02:27:24Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:06:57Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8c30b571303fffd06615aeeb3143112c7bb00f2a'/>
<id>urn:sha1:8c30b571303fffd06615aeeb3143112c7bb00f2a</id>
<content type='text'>
Some of the LPC code is common to several Intel LPC devices. Move it into a
common location.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Move microcode code to a common location</title>
<updated>2016-03-17T02:27:24Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:06:54Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9e66506d33eac67bfa814ccba1c9ccd06bb5b107'/>
<id>urn:sha1:9e66506d33eac67bfa814ccba1c9ccd06bb5b107</id>
<content type='text'>
This code is used on several Intel CPUs. Move it into a common location.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Move cache-as-RAM code into a common location</title>
<updated>2016-03-17T02:27:24Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:06:53Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1223d737a38dab7f05e7d62a3c931e28aa1e1495'/>
<id>urn:sha1:1223d737a38dab7f05e7d62a3c931e28aa1e1495</id>
<content type='text'>
This cache-as-RAM (CAR) code is common to several Intel chips. Create a new
intel_common directory and move it in there.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
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