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<title>u-boot.git/arch/x86/cpu/intel_common/car2_uninit.S, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/cpu/intel_common/car2_uninit.S?h=main</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/x86/cpu/intel_common/car2_uninit.S?h=main'/>
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<updated>2019-12-15T03:44:18Z</updated>
<entry>
<title>x86: Add support for newer CAR schemes</title>
<updated>2019-12-15T03:44:18Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-12-07T04:42:25Z</published>
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<id>urn:sha1:f45e747d6d0b107992e8aed74c001034c8a6f1a1</id>
<content type='text'>
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
Add support for these along with suitable configuration options.

To make the code cleaner, adjust a few definitions in processor.h so that
they can be used from assembler.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
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