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<title>u-boot.git/arch/x86/cpu/intel_common, branch v2016.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/cpu/intel_common?h=v2016.09</id>
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<updated>2016-08-30T01:26:05Z</updated>
<entry>
<title>x86: ivybridge: Allow microcode to be collated</title>
<updated>2016-08-30T01:26:05Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-07-26T00:58:58Z</published>
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<id>urn:sha1:e6294e0579897a682a823aefc99fe416c78aaf6e</id>
<content type='text'>
Generally the microcode is combined into a single block only (and removed
from the device tree) when there are multiple blocks. But this is not a
requirement.

Adjust the ivybridge code to avoid assuming this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add debugging when a microcode update fails</title>
<updated>2016-08-30T01:26:05Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-07-26T00:58:57Z</published>
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<id>urn:sha1:fda4fa8195bab36879272e92973a7ef39e759795</id>
<content type='text'>
Add a debug() at this point to help figure out what is wrong.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Heiko Schocher&lt;hs@denx.de&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>dm: Rename disk uclass to ahci</title>
<updated>2016-05-17T15:54:43Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-05-01T17:35:52Z</published>
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<id>urn:sha1:a219639d4216e59a0c55f0b7d2c8a21f9cb0bb06</id>
<content type='text'>
This started as 'ahci' and was renamed to 'disk' during code review. But it
seems that this is too generic. Now that we have a 'blk' uclass, we can use
that as the generic piece, and revert to ahci for this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Add common SDRAM-init code</title>
<updated>2016-03-17T02:27:27Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-16T13:44:37Z</published>
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<id>urn:sha1:65dd1507e3b744954d43811a1e4d9f194d1bda64</id>
<content type='text'>
The code to call the memory reference code is common to several Intel CPUs.
Add common code for performing this init. Intel calls this 'Pre-EFI-Init'
(PEI), where EFI stands for Extensible Firmware Interface.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Move common PCH code into a common place</title>
<updated>2016-03-17T02:27:27Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-16T13:44:36Z</published>
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<id>urn:sha1:7e4a6ae62c7ee567ae43e94445e561b3ec8343b9</id>
<content type='text'>
The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Update microcode for secondary CPUs</title>
<updated>2016-03-17T02:27:25Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:07:11Z</published>
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<id>urn:sha1:e77b62e2906affb94f442ce7735762883f8147af</id>
<content type='text'>
Each CPU needs to have its microcode loaded. Add support for this so that
all CPUs will have the same version.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Record the CPU details when starting each core</title>
<updated>2016-03-17T02:27:25Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:07:09Z</published>
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<id>urn:sha1:6bcb675b2f6a3251d0107673949988c619ec18ec</id>
<content type='text'>
As each core starts up, record its microcode version and CPU ID so these can
be presented with the 'cpu detail' command.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Move Intel Management Engine code to a common place</title>
<updated>2016-03-17T02:27:24Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:07:00Z</published>
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<id>urn:sha1:8b900a417527d9ad94dc4aab2c9d6717bdc50b33</id>
<content type='text'>
Some of the Intel ME code is common to several Intel CPUs. Move it into a
common location. Add a header file for report_platform.c also.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
[squashed in http://patchwork.ozlabs.org/patch/598372/]
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Rename PORT_RESET to IO_PORT_RESET</title>
<updated>2016-03-17T02:27:24Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:06:59Z</published>
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<id>urn:sha1:2a605d4d8889ac5dd4c806b3a37ba75a80716e46</id>
<content type='text'>
This same name is used in USB. Add a prefix to distinguish it.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Move common CPU code to its own place</title>
<updated>2016-03-17T02:27:24Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:06:58Z</published>
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<id>urn:sha1:50dd3da0042b4502bab622ef7f72f628b842cf26</id>
<content type='text'>
Some of the Intel CPU code is common to several Intel CPUs. Move it into a
common location along with required declarations.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
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