<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/arch/x86/cpu/intel_common, branch v2020.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/cpu/intel_common?h=v2020.07</id>
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<updated>2020-06-02T01:16:13Z</updated>
<entry>
<title>x86: spi: Add a way to access the SPI mapping via registers</title>
<updated>2020-06-02T01:16:13Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-27T12:58:46Z</published>
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<id>urn:sha1:8e2922e357fe0157593063d46f8e9bd2c25a00e0</id>
<content type='text'>
At present the PCI BDF (bus/device/function) is needed to access the SPI
mapping, since the registers are at BAR0. This doesn't work when PCI
auto-config has not been done yet, since BARs are unassigned.

Add another way to find the mapping, using the MMIO base, if the caller
knows this.

Also add a missing function comment.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>common: Drop linux/bitops.h from common header</title>
<updated>2020-05-19T01:19:23Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:13Z</published>
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<id>urn:sha1:cd93d625fd751d55c729c78b10f82109d56a5f1d</id>
<content type='text'>
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>common: Drop log.h from common header</title>
<updated>2020-05-19T01:19:18Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:05Z</published>
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<id>urn:sha1:f7ae49fc4f363a803dab3be078e93ead8e75a8e9</id>
<content type='text'>
Move this header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>common: Drop init.h from common header</title>
<updated>2020-05-18T21:33:33Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-10T17:40:02Z</published>
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<id>urn:sha1:691d719db7183dfb1d1360efed4c5e9f6899095f</id>
<content type='text'>
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Allow building an SPL image</title>
<updated>2020-05-04T07:28:28Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-05-01T03:21:43Z</published>
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<id>urn:sha1:b4d4f592b243d08791ce582073710444ede48446</id>
<content type='text'>
Make a few adjustments to allow us to build an SPL image for coreboot.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: apl: Move p2sb ofdata reading to the correct method</title>
<updated>2020-04-16T06:36:28Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-04-08T22:57:28Z</published>
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<id>urn:sha1:163085308576139ac0b0c65e3b81be78ab890aa9</id>
<content type='text'>
With P2SB the initial BAR (base-address register) is set up by TPL and
this is used unchanged right through U-Boot.

At present the reading of this address is split between the ofdata() and
probe() methods. There are a few problems that are unique to the p2sb.
One is that its children need to call pcr_read32(), etc. which needs to
have the p2sb address correct. Also some of its children are pinctrl
devices and pinctrl is used when any device is probed. So p2sb really
needs to get its base address set up in ofdata_to_platdata(), before it is
probed.

Another point is that reading the p2sb BAR will not work if the p2sb is
hidden. The FSP-S seems to hide it, presumably to avoid confusing PCI
enumeration.

Reading ofdata in ofdata_to_platdata() is the correct place anyway, so
this is easy to fix.

Move the code into one place and use the early-regs property in all cases
for simplicity and to avoid needing to probe any PCI devices just to read
the BAR.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Wolfgang Wallner &lt;wolfgang.wallner@br-automation.com&gt;
Tested-by: Wolfgang Wallner &lt;wolfgang.wallner@br-automation.com&gt;
</content>
</entry>
<entry>
<title>x86: p2sb: Drop 'apl' prefix</title>
<updated>2020-03-05T10:25:21Z</updated>
<author>
<name>Wolfgang Wallner</name>
<email>wolfgang.wallner@br-automation.com</email>
</author>
<published>2020-02-18T14:32:10Z</published>
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<id>urn:sha1:5a9d7f9c919d8c9009d5c75a9c2dcdf5214a4589</id>
<content type='text'>
Drop the Apollo Lake prefix 'apl' from the functions, types and
variables in the P2SB driver.

The P2SB is not Apollo Lake specific, and as such it was moved in
commit 2999846c1127 ("x86: Move P2SB from Apollo Lake to a more generic
location") from the Apollo Lake folder to the intel_common folder.

Signed-off-by: Wolfgang Wallner &lt;wolfgang.wallner@br-automation.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm</title>
<updated>2020-02-11T15:58:41Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2020-02-11T15:58:41Z</published>
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<id>urn:sha1:9a8942b53d57149754e0dfc975e0d92d1afd4087</id>
<content type='text'>
sandbox conversion to SDL2
TPM TEE driver
Various minor sandbox video enhancements
New driver model core utility functions
</content>
</entry>
<entry>
<title>x86: itss: Add of-platdata support</title>
<updated>2020-02-07T14:45:35Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-02-06T16:54:59Z</published>
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<id>urn:sha1:d9a5fad80857005703d46b6ea27217baa17eb142</id>
<content type='text'>
Allow this driver to be used in TPL by setting up the interrupt type
correctly.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Give each driver an IRQ type</title>
<updated>2020-02-07T14:45:35Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-02-06T16:54:58Z</published>
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<id>urn:sha1:69c2dc937a53f4f35688c1289720625e002f3791</id>
<content type='text'>
Add an IRQ type to each driver and use irq_first_device_type() to find
and probe the correct one.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
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