u-boot.git/arch/x86/cpu, branch v2015.07

x86: baytrail: pci region 3 is not always mapped to end of ram

2015-06-04T09:03:18Z

Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF and additional SDRAM is mapped from 0x100000000 and up. There is a physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses. Because of this, PCI region 3 should only try to use up to the amount of SDRAM or 0x80000000, which ever is less. Signed-off-by: Andrew Bradford Reviewed-by: Bin Meng Acked-by: Simon Glass

x86: qemu: Implement PIRQ routing

2015-06-04T09:03:18Z

Support QEMU PIRQ routing via device tree on both i440fx and q35 platforms. With this commit, Linux booting on QEMU from U-Boot has working ATA/SATA, USB and ethernet. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: coreboot: Control I/O port 0xb2 writing via device tree

2015-06-04T09:03:18Z

Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes U-Boot to hang on QEMU q35 target. We introduce a config option in the device tree "u-boot,no-apm-finalize" under /config node if we don't want to do that. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: coreboot: Fix cosmetic issues

2015-06-04T09:03:17Z

Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: qemu: Adjust VGA initialization

2015-06-04T08:39:40Z

As VGA option rom needs to run at C segment, although QEMU PAM emulation seems to only guard E/F segments, for correctness, move VGA initialization after PAM decode C/D/E/F segments. Also since we already tested QEMU targets to differentiate I440FX and Q35 platforms, change to locate the VGA device via hardcoded b.d.f instead of dynamic search for its vendor id & device id pair. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: qemu: Enable legacy IDE I/O ports decode

2015-06-04T08:39:39Z

QEMU always decode legacy IDE I/O ports on PIIX chipset. However Linux ata_piix driver does sanity check to see whether legacy ports decode is turned on. To make Linux ata_piix driver happy, turn on the decode via IDE_TIMING register. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: qemu: Turn on legacy segments decode

2015-06-04T08:39:39Z

By default the legacy segments C/D/E/F do not decode to system RAM. Turn on the decode via Programmable Attribute Map (PAM) registers so that we can write configuration tables in the F segment. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: Do sanity test on pirq table before writing

2015-06-04T08:39:39Z

If pirq_routing_table points to NULL, that means U-Boot fails to generate the table before in create_pirq_routing_table(), so we test it against NULL before actually writing it. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: quark: Implement PIRQ routing

2015-06-04T08:39:39Z

Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: Refactor PIRQ routing support

2015-06-04T08:39:39Z

PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng Acked-by: Simon Glass