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<title>u-boot.git/arch/x86/cpu, branch v2016.03</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/cpu?h=v2016.03</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/x86/cpu?h=v2016.03'/>
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<updated>2016-02-21T05:42:52Z</updated>
<entry>
<title>x86: Add Intel Cougar Canyon 2 board</title>
<updated>2016-02-21T05:42:52Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-17T08:16:25Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a2e3b05e16c96ccc5929d60457938cd96912d758'/>
<id>urn:sha1:a2e3b05e16c96ccc5929d60457938cd96912d758</id>
<content type='text'>
This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: ivybridge: bd82x6x: Support FSP enabled configuration</title>
<updated>2016-02-21T05:42:52Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-17T08:16:24Z</published>
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<id>urn:sha1:87077e97d1a72286871d03a6f06903245b9caacd</id>
<content type='text'>
Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif,
and enable the build for both FSP and non-FSP configurations.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: ivybridge: Add FSP support</title>
<updated>2016-02-21T05:42:52Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-17T08:16:21Z</published>
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<id>urn:sha1:437413962744cc9c80551ca253a20472856551f2</id>
<content type='text'>
IvyBridge FSP package is built with a base address at 0xfff80000,
and does not use UPD data region. This adds basic FSP support.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: fix memalign() parameter order</title>
<updated>2016-02-21T05:42:51Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2016-02-12T21:27:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4fd64d02b2bb7fe583c1246c79b9658223d96442'/>
<id>urn:sha1:4fd64d02b2bb7fe583c1246c79b9658223d96442</id>
<content type='text'>
Purely by code inspection, it looks like the parameter order to memalign()
is swapped; its parameters are (align, size). 4096 is a likely desired
alignment, and a variable named size sounds like a size:-)

Fixes: 45b5a37836d5 ("x86: Add multi-processor init")
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging</title>
<updated>2016-02-08T14:48:04Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-02-08T14:48:04Z</published>
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<id>urn:sha1:57dc53a72460e8e301fa1cc7951b41db8e731485</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Use correct spelling of "U-Boot"</title>
<updated>2016-02-06T11:00:59Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-06T03:30:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a187559e3d586891c917279044c5386d1b2adc6e'/>
<id>urn:sha1:a187559e3d586891c917279044c5386d1b2adc6e</id>
<content type='text'>
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Heiko Schocher &lt;hs@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>x86: quark: Use Quark's own PCI config APIs</title>
<updated>2016-02-05T04:47:23Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-02T13:58:02Z</published>
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<id>urn:sha1:5a257df702e5702f46fca548d0899c65e90df947</id>
<content type='text'>
There are still two places in Quark's MRC codes that use the generic
legacy PCI APIs, but as we are phasing out these legacy APIs, switch
to use Quark's own PCI config routines.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: pci: Drop legacy PCI APIs</title>
<updated>2016-02-05T04:47:23Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-01T09:40:58Z</published>
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<id>urn:sha1:3857ed015f8bd9331a8eaeb9b887448e2caff15c</id>
<content type='text'>
Now that we have converted all x86 codes to use DM PCI APIs,
drop those legacy ones.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: pci: Use DM PCI APIs in pci_assign_irqs()</title>
<updated>2016-02-05T04:47:22Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-01T09:40:57Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=58316f9b9f1061f988b91ee49c69370eead7d8ca'/>
<id>urn:sha1:58316f9b9f1061f988b91ee49c69370eead7d8ca</id>
<content type='text'>
Drop legacy PCI APIs usage in pci_assign_irqs() as well.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: qemu: Convert to use DM PCI API</title>
<updated>2016-02-05T04:47:22Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-01T09:40:56Z</published>
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<id>urn:sha1:6039200c65e645c81032e0fe20f036f83bbc1c46</id>
<content type='text'>
Use pci_[read|write]_config intead of x86_pci_[read|write]_config.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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