u-boot.git/arch/x86/cpu, branch v2016.07

x86: coreboot: Remove the dummy pch driver

2016-06-29T02:08:15Z

There is a dummy pch driver in the coreboot directory. This causes drivers of its children fail to function due to empty ops. Remove the whole file since it is no longer needed. Signed-off-by: Bin Meng Reviewed-by: Simon Glass

x86: Probe pinctrl driver in cpu_init_r()

2016-06-12T04:19:35Z

At present pinctrl driver gets probed in ich6_gpio driver's probe routine, which has two issues: - Pin's PADs only gets configured when GPIO driver is probed, which is not done by default. This leaves the board in a partially functional state as we must initialize PADs correctly to get perepherals fully working. - The probe routine of pinctrl driver is called multiple times, as normally there are multiple GPIO controllers. It should really be called just once. Move the call to syscon_get_by_driver_data() from ich6_gpio driver to cpu_init_r(). Signed-off-by: Bin Meng Reviewed-by: Stefan Roese Reviewed-by: Simon Glass Reviewed-by: George McCollister Tested-by: George McCollister

x86: baytrail: acpi: Fix I/O APIC ID in the MADT table

2016-05-30T02:21:12Z

So far this is hardcoded to 2, but it should really be read from the I/O APIC register. Signed-off-by: Bin Meng Reviewed-by: Simon Glass

x86: quark: Generate ACPI FADT/MADT tables

2016-05-30T02:21:12Z

Generate quark platform-specific FADT/MADT tables. Signed-off-by: Bin Meng Reviewed-by: Simon Glass

x86: broadwell: Correct I/O APIC ID

2016-05-23T07:27:42Z

Currently ID 2 is assgined to broadwell I/O APIC, however per chromebook_samus.dts 2 is the core#2 LAPIC ID. Now we change I/O APIC ID to 4 to avoid conflict. Signed-off-by: Bin Meng Reviewed-by: Simon Glass

x86: quark: Assign a unique I/O APIC ID

2016-05-23T07:27:42Z

After power-on, both LAPIC and I/O APIC appear with the same APIC ID zero, which creates an ID conflict. When generating MP table, U-Boot reports zero as the LAPIC ID in the processor entry, and zero as the I/O APIC ID in the I/O APIC as well as the I/O interrupt assignment entries. Such MP table confuses Linux kernel and finally a kernel panic is seen during boot: BUG: unable to handle kernel paging request at ffff9000 IP: [] native_io_apic_write+0x22/0x30 *pdpt = 00000000014fb001 *pde = 00000000014ff067 *pte = 0000000000000000 Oops: 0002 [#1] Modules linked in: Pid: 1, comm: swapper Tainted: G W 3.8.7 #3 intel galileo/galileo EIP: 0060:[] EFLAGS: 00010086 CPU: 0 EIP is at native_io_apic_write+0x22/0x30 ... Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 Signed-off-by: Bin Meng Reviewed-by: Simon Glass

x86: Call lapic_setup() in interrupt_init()

2016-05-23T07:27:41Z

Let's configure LAPIC in a common place - interrupt_init(). Signed-off-by: Bin Meng Reviewed-by: Simon Glass

x86: Remove SMP limitation in lapic_setup()

2016-05-23T07:27:41Z

At present LAPIC is enabled and configured as virtual wire mode in lapic_setup() only when CONFIG_SMP is on. This limitation is however not necessary as for uniprocessor this is still needed. Signed-off-by: Bin Meng Reviewed-by: Simon Glass

x86: Don't touch IA32_APIC_BASE MSR on Intel Quark

2016-05-23T07:27:41Z

Intel Quark processor core provides an integrated Local APIC but does not support the IA32_APIC_BASE MSR. As a result, the Local APIC is always globally enabled and the Local APIC base address is fixed at 0xfee00000. Attempting to access the IA32_APIC_BASE MSR causes a general protection fault. Signed-off-by: Bin Meng Reviewed-by: Simon Glass

x86: Reserve configuration tables in high memory

2016-05-23T07:18:00Z

When SeaBIOS is on, reserve configuration tables in reserve_arch(). Signed-off-by: Bin Meng Reviewed-by: Simon Glass