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<title>u-boot.git/arch/x86/cpu, branch v2016.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/cpu?h=v2016.09</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/x86/cpu?h=v2016.09'/>
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<updated>2016-08-30T01:26:05Z</updated>
<entry>
<title>x86: Add debugging when cpu_common_init() fails</title>
<updated>2016-08-30T01:26:05Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-07-26T00:58:59Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4cc00f0611c4b491f6dd1f6a5582d24a41f12769'/>
<id>urn:sha1:4cc00f0611c4b491f6dd1f6a5582d24a41f12769</id>
<content type='text'>
Add a debug() at this point to help figure out what is wrong.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: ivybridge: Allow microcode to be collated</title>
<updated>2016-08-30T01:26:05Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-07-26T00:58:58Z</published>
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<id>urn:sha1:e6294e0579897a682a823aefc99fe416c78aaf6e</id>
<content type='text'>
Generally the microcode is combined into a single block only (and removed
from the device tree) when there are multiple blocks. But this is not a
requirement.

Adjust the ivybridge code to avoid assuming this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add debugging when a microcode update fails</title>
<updated>2016-08-30T01:26:05Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-07-26T00:58:57Z</published>
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<id>urn:sha1:fda4fa8195bab36879272e92973a7ef39e759795</id>
<content type='text'>
Add a debug() at this point to help figure out what is wrong.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Heiko Schocher&lt;hs@denx.de&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: baytrail: Add SIO HS-UART clock setup</title>
<updated>2016-08-16T03:44:09Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2016-07-19T05:41:25Z</published>
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<id>urn:sha1:d7b935bf62bafdf5fbe4734c7536754948958890</id>
<content type='text'>
To support the BayTrail internal SIO HS UART, the internal UART clock
needs to get configured. This patch adds support for this clock
configuration which will be done, if the PCI device(s) are found.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-x86</title>
<updated>2016-07-12T12:15:17Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-07-12T12:15:17Z</published>
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<id>urn:sha1:b8e599746cac1833328bc3a8e37eeefe346baf90</id>
<content type='text'>
</content>
</entry>
<entry>
<title>x86: link: Correct a failure in DRAM init</title>
<updated>2016-07-12T05:59:45Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-07-11T15:30:55Z</published>
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<id>urn:sha1:9532fe3b40ddf66ef976dee3d5cf1d8b3396bf4d</id>
<content type='text'>
With the change to set up pinctrl after relocation, link fails to boot. Add
a special case in the link code to handle this.

Fixes: d8906c1f (x86: Probe pinctrl driver in cpu_init_r())

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: quark: Introduce ACPI global NVS</title>
<updated>2016-07-12T05:46:01Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-06-17T09:13:15Z</published>
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<id>urn:sha1:cf7108b320e1851b829d6adc9bd4f4462c5f5072</id>
<content type='text'>
This introduces quark-specific ACPI global NVS structure, defined in
both C header file and ASL file.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: baytrail: Introduce ACPI global NVS</title>
<updated>2016-07-12T05:46:01Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-06-17T09:13:14Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2047390abc04b921764bd23eeffc0d3e83a2a674'/>
<id>urn:sha1:2047390abc04b921764bd23eeffc0d3e83a2a674</id>
<content type='text'>
This introduces baytrail-specific ACPI global NVS structure, defined in
both C header file and ASL file.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: George McCollister &lt;george.mccollister@gmail.com&gt;
Tested-by: George McCollister &lt;george.mccollister@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: baytrail: Introduce a Kconfig option for the internal UART</title>
<updated>2016-07-12T05:46:01Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-06-15T04:33:23Z</published>
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<id>urn:sha1:377656b2cc3be3e704fc574041669a4a84ea6bb8</id>
<content type='text'>
There are quite a number of BayTrail boards that uses an external
SuperIO chipset to provide the legacy UART. For such cases, it's
better to have a Kconfig option to enable the internal UART.

So far BayleyBay and MinnowMax boards are using internal UART as
the U-Boot console, enable this on these two boards.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: fdt: Drop the unused compatible strings in fdtdec</title>
<updated>2016-07-11T20:06:44Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-06-19T23:33:11Z</published>
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<id>urn:sha1:6cd2602d61fc4bc172fd99dcbe9b930428992331</id>
<content type='text'>
We have drivers for several more devices now, so drop the strings which are
no-longer used.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
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