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<title>u-boot.git/arch/x86/cpu, branch v2018.03</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/cpu?h=v2018.03</id>
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<updated>2018-03-05T15:16:28Z</updated>
<entry>
<title>libfdt: move headers to &lt;linux/libfdt.h&gt; and &lt;linux/libfdt_env.h&gt;</title>
<updated>2018-03-05T15:16:28Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2018-03-04T16:20:11Z</published>
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<id>urn:sha1:b08c8c4870831c9315dcae237772238e80035bd5</id>
<content type='text'>
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.

This commit moves the header code:
  include/libfdt.h         -&gt; include/linux/libfdt.h
  include/libfdt_env.h     -&gt; include/linux/libfdt_env.h

and replaces include directives:
  #include &lt;libfdt.h&gt;      -&gt; #include &lt;linux/libfdt.h&gt;
  #include &lt;libfdt_env.h&gt;  -&gt; #include &lt;linux/libfdt_env.h&gt;

Reported-by: Thomas Petazzoni &lt;thomas.petazzoni@bootlin.com&gt;
Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
</content>
</entry>
<entry>
<title>x86: quark: Fix unused warnings</title>
<updated>2018-01-30T14:34:38Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-01-27T20:13:47Z</published>
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<id>urn:sha1:d0c0752addcb82fbc74c43842a58cca34d22de00</id>
<content type='text'>
The variable t_rfc is never used, so drop it.  The variables ddr_wctl
and ddr_wcmd are only used in certain manual instances, so guard their
declaration by the same check as their use.

Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>ata: Migrate CONFIG_SCSI_AHCI to Kconfig</title>
<updated>2017-12-12T23:13:19Z</updated>
<author>
<name>Tuomas Tynkkynen</name>
<email>tuomas.tynkkynen@iki.fi</email>
</author>
<published>2017-12-08T13:36:19Z</published>
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<id>urn:sha1:9fd95ef0d39819fb27441fdd0f1b15b05d9b5085</id>
<content type='text'>
And use 'imply' liberally.

Signed-off-by: Tuomas Tynkkynen &lt;tuomas.tynkkynen@iki.fi&gt;
</content>
</entry>
<entry>
<title>x86: don't compare pointers to 0</title>
<updated>2017-11-30T05:50:17Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2017-11-20T18:45:56Z</published>
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<id>urn:sha1:39670c341f0598dd00e5124deb5b479bf674b949</id>
<content type='text'>
x86_vendor_name is defined as

static const char *const x86_vendor_name[]

So its elements should not be compared to 0.

Remove superfluous paranthesis.

Problem identified with Coccinelle.

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: qemu: Move Cache-As-RAM memory from area mapped to ROM</title>
<updated>2017-11-30T05:50:17Z</updated>
<author>
<name>Anton Gerasimov</name>
<email>anton@advancedtelematic.com</email>
</author>
<published>2017-11-14T17:47:16Z</published>
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<id>urn:sha1:80f3425c5733bbf4459db86e60dc363342bdc2d6</id>
<content type='text'>
ROM has been made read-only in qemu recently (namely commit 208fa0e4:
"pc: make 'pc.rom' readonly when machine has PCI enabled"). So this
patch restores compatibility between U-Boot and qemu.

Signed-off-by: Anton Gerasimov &lt;anton@advancedtelematic.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
[bmeng: mention qemu commit title in the commit message]
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: braswell: cherryhill: Update dts for SPI lock down</title>
<updated>2017-10-27T07:13:47Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-10-19T01:20:58Z</published>
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<id>urn:sha1:4c9f4c5ee4ac15a285f3ceb25752432990084dc1</id>
<content type='text'>
Intel Braswell FSP requires SPI controller settings to be locked down,
let's do this in the chrryhill.dts and remove previous Kconfig option.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>env: x86: braswell: Set ENV_IS_IN_SPI_FLASH as default</title>
<updated>2017-10-27T07:13:47Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-10-19T01:20:54Z</published>
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<id>urn:sha1:3a856473fdb05f8c20686f6240781ecb2c0c1b61</id>
<content type='text'>
Imply does not work for a Kconfig choice. Update ENV_IS_IN_SPI_FLASH
to be the default one for Intel Braswell.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: braswell: Fix unexpected crash during Linux kernel boot</title>
<updated>2017-10-27T07:13:47Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-10-19T01:20:53Z</published>
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<id>urn:sha1:4a5a7fcac24498aa1535a467f0739e2fda5b4324</id>
<content type='text'>
It was observed that when booting Linux kernel on Intel Cherry Hill
board, unexpected crash happens quite randomly. Sometimes kernel
just oops, while sometimes kernel throws MCE errors and hangs:

  mce: [Hardware Error]: Machine check events logged
  mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 4: c400000000010151
  mce: [Hardware Error]: TSC 0 ADDR 130f3f2c0
  mce: [Hardware Error]: PROCESSOR 0:406c3 TIME 1508160686 SOCKET 0 APIC 0 microcode 363

This looks like a hardware error per mcelog. After debugging, it
seems turning off turbo mode on the processor does not expose this
behavior, although U-Boot runs OK with turbo mode on. Suspect it is
related to an errata of Braswell processor.

To fix this, remove the Braswell cpu driver which does the turbo
mode configuration, and switch to use the generic cpu-x86 driver.
Also there is a configuration option in the FSP that turns on the
turbo mode and that has been turned off too.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: baytrail: fsp: Move Azalia update codes to board</title>
<updated>2017-10-19T03:37:51Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-10-13T08:30:06Z</published>
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<id>urn:sha1:83262f99cd3619336b0d48257bc6595b7610a134</id>
<content type='text'>
Azalia configuration may be different across boards, hence it's not
appropriate to do that in the SoC level. Instead, let's make the
SoC update_fsp_azalia_configs() routine as a weak version, and do
the actual work in the board codes.

So far it seems only som-db5800-som-6867 board enables the Azalia.
Move the original codes into som-db5800-som-6867.c.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>x86: baytrail: fsp: Use a function to update the Azalia config pointer</title>
<updated>2017-10-19T03:37:51Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-10-13T08:30:05Z</published>
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<id>urn:sha1:f6859558ca4e18d3a76fafb85924a50026be82fb</id>
<content type='text'>
At present we directly pass the Azalia config pointer to the FSP UPD.
This updates to use a function to do the stuff, like Braswell does.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
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