u-boot.git/arch/x86/dts/microcode/m01406c3363.dtsi, branch nextUnnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/arch/x86/dts/microcode/m01406c3363.dtsi?h=next2017-09-16T06:57:44Zx86: braswell: Add microcode for B0/C0/D0 stepping SoC2017-09-16T06:57:44ZBin Mengbmeng.cn@gmail.com2017-08-16T05:41:59Zurn:sha1:e61a2687b3ed9661755a33146530a51320cdd76b
This adds microcode device tree fragment for Braswell B0 (406C2),
C0 (406C3) and D0 (406C4) stepping SoC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>