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<updated>2016-01-13T04:20:15Z</updated>
<entry>
<title>x86: ivybridge: Add microcode blobs for all the steppings</title>
<updated>2016-01-13T04:20:15Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-12-11T10:55:47Z</published>
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<id>urn:sha1:33fb6c0100de6dbc79d0237418941cc40e94b16d</id>
<content type='text'>
This adds microcode blobs created from Intel FSP package for the
Chief River platform. They are for all the Ivy Bridge steppings:
306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the
306a9 which is already in the U-Boot tree.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
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