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<title>u-boot.git/arch/x86/include/asm/global_data.h, branch v2015.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<updated>2014-12-14T05:32:05Z</updated>
<entry>
<title>x86: Support Intel FSP initialization path in start.S</title>
<updated>2014-12-14T05:32:05Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2014-12-12T13:05:31Z</published>
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<id>urn:sha1:bceb9f0fc80c71b8b2a7371288199cdacca1bad9</id>
<content type='text'>
Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two routines have to be called
before U-Boot jumping to board_init_f in start.S.

The FspInit() will return several memory blocks called Hand Off
Blocks (HOBs) whose format is described in Platform Initialization
(PI) specification (part of the UEFI specication) to the bootloader.
Save this HOB address to the U-Boot global data for later use.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: ivybridge: Implement SDRAM init</title>
<updated>2014-11-21T06:34:15Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-11-13T05:42:28Z</published>
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<id>urn:sha1:65dd74a674d636afcc14594c8308ff516e95a445</id>
<content type='text'>
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
the board directory and the SDRAM SPD information in the device tree. This
also needs the Intel Management Engine (me.bin) to work. Binary blobs
everywhere: so far we have MRC, ME and microcode.

SDRAM init works by setting up various parameters and calling the MRC. This
in turn does some sort of magic to work out how much memory there is and
the timing parameters to use. It also sets up the DRAM controllers. When
the MRC returns, we use the information it provides to map out the
available memory in U-Boot.

U-Boot normally moves itself to the top of RAM. On x86 the RAM is not
generally contiguous, and anyway some RAM may be above 4GB which doesn't
work in 32-bit mode. So we relocate to the top of the largest block of
RAM we can find below 4GB. Memory above 4GB is accessible with special
functions (see physmem).

It would be possible to build U-Boot in 64-bit mode but this wouldn't
necessarily provide any more memory, since the largest block is often below
4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large
ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit
kernels directly so this does not pose a limitation in that area. Also there
are probably parts of U-Boot that will not work correctly in 64-bit mode.
The MRC is one.

There is some work remaining in this area. Since memory init is very slow
(over 500ms) it is possible to save the parameters in SPI flash to speed it
up next time. Suspend/resume support is not fully implemented, or at least
it is not efficient.

With this patch, link boots to a prompt.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: ivybridge: Add support for early GPIO init</title>
<updated>2014-11-21T06:34:14Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-11-13T05:42:24Z</published>
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<id>urn:sha1:1b4f25ff8e6967f14494c5a0d173758a7a3ac279</id>
<content type='text'>
When not relying on Coreboot for GPIO init the GPIOs must be set up
correctly. This is currently done statically through a rather ugly method.
As the GPIOs are figured out they can be moved to the device tree and set
up as needed rather than all at the start.

In this implementation, board files should call ich_gpio_set_gpio_map()
before the GPIO driver is used in order to provide the GPIO information.
We use the early PCI interface so that this driver can now be used before
relocation.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: ivybridge: Add early init for PCH devices</title>
<updated>2014-11-21T06:34:14Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-11-13T05:42:23Z</published>
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<id>urn:sha1:8e0df066ffc40fde4cf43014114f8e472b8b9bd6</id>
<content type='text'>
Many PCH devices are hard-coded to a particular PCI address. Set these
up early in case they are needed.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Support use of PCI before relocation</title>
<updated>2014-11-21T06:34:12Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-11-13T05:42:12Z</published>
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<id>urn:sha1:7430f1086429fa93e80c3951baac90e1c578898a</id>
<content type='text'>
Add support for using PCI before SDRAM is available, using early malloc()
and global_data.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Save TSC frequency in the global data</title>
<updated>2014-11-21T06:24:10Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2014-11-09T14:19:35Z</published>
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<id>urn:sha1:258b1357c6b324b0a45ca0c1cf3dfd1ef1b4c5c4</id>
<content type='text'>
Return the saved TSC frequency in get_tbclk_mhz().

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Do CPU identification in the early phase</title>
<updated>2014-11-21T06:24:10Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2014-11-09T14:18:56Z</published>
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<id>urn:sha1:52f952bf5ecebc1de01269557591bad4ac62a01a</id>
<content type='text'>
The CPU identification happens in x86_cpu_init_f() and corresponding
fields are saved in the global data for later use.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Save the BIST value on reset</title>
<updated>2014-11-21T06:24:10Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-11-06T20:20:10Z</published>
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<id>urn:sha1:f67cd51e654ba6498230314b6e82b4dbbd4bfca7</id>
<content type='text'>
The built in self test value is available in register eax on start-up. Save
it so that it can be accessed later. Unfortunately we must wait until the
global_data is available before we can do this, so there is a little bit of
shuffling to keep it around.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>Add GPL-2.0+ SPDX-License-Identifier to source files</title>
<updated>2013-07-24T13:44:38Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2013-07-08T07:37:19Z</published>
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<id>urn:sha1:1a4596601fd395f3afb8f82f3f840c5e00bdd57a</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>x86: Support tracing function</title>
<updated>2013-06-26T14:18:56Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-06-11T18:14:52Z</published>
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<id>urn:sha1:d8819f94d58d8c94c619431bc34232a52b2d9a6b</id>
<content type='text'>
Some changes are needed to x86 timer functions to support tracing. Add
these so that the feature works correctly.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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