u-boot.git/arch/x86/include/asm, branch v2015.07

x86: gpio: add pinctrl support from the device tree

2015-06-04T09:32:08Z

Every pin can be configured now from the device tree. A dt-bindings has been added to describe the different property available. Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975 Signed-off-by: Gabriel Huau Acked-by: Simon Glass

x86: coreboot: Fix cosmetic issues

2015-06-04T09:03:17Z

Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: qemu: Adjust VGA initialization

2015-06-04T08:39:40Z

As VGA option rom needs to run at C segment, although QEMU PAM emulation seems to only guard E/F segments, for correctness, move VGA initialization after PAM decode C/D/E/F segments. Also since we already tested QEMU targets to differentiate I440FX and Q35 platforms, change to locate the VGA device via hardcoded b.d.f instead of dynamic search for its vendor id & device id pair. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: qemu: Enable legacy IDE I/O ports decode

2015-06-04T08:39:39Z

QEMU always decode legacy IDE I/O ports on PIIX chipset. However Linux ata_piix driver does sanity check to see whether legacy ports decode is turned on. To make Linux ata_piix driver happy, turn on the decode via IDE_TIMING register. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: qemu: Turn on legacy segments decode

2015-06-04T08:39:39Z

By default the legacy segments C/D/E/F do not decode to system RAM. Turn on the decode via Programmable Attribute Map (PAM) registers so that we can write configuration tables in the F segment. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: quark: Implement PIRQ routing

2015-06-04T08:39:39Z

Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: Refactor PIRQ routing support

2015-06-04T08:39:39Z

PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: Support QEMU x86 targets

2015-06-04T08:39:38Z

This commit introduces the initial U-Boot support for QEMU x86 targets. U-Boot can boot from coreboot as a payload, or directly without coreboot. Signed-off-by: Bin Meng Acked-by: Simon Glass Tested-by: Simon Glass Merged in patch 'x86: qemu: Add CMD_NET to qemu-x86_defconfig https://patchwork.ozlabs.org/patch/479745/

x86: Add a CPU driver for baytrail

2015-04-30T22:13:50Z

This driver supports multi-core init and sets up the CPU frequencies correctly. Signed-off-by: Simon Glass Reviewed-by: Bin Meng

x86: Allow CPUs to be set up after relocation

2015-04-30T22:13:48Z

This permits init of additional CPU cores after relocation and when driver model is ready. Signed-off-by: Simon Glass Reviewed-by: Bin Meng