u-boot.git/arch/x86/include, branch v2015.01

x86: Clean up the FSP support codes

2014-12-19T00:26:08Z

This is the follow-on patch to clean up the FSP support codes: - Remove the _t suffix on the structures defines - Use __packed for structure defines - Use U-Boot's assert() - Use standard bool true/false - Remove read_unaligned64() - Use memcmp() in the compare_guid() - Remove the cast in the memset() call - Replace some magic numbers with macros - Use panic() when no valid FSP image header is found - Change some FSP utility routines to use an fsp_ prefix - Add comment blocks for asm_continuation and fsp_init_done - Remove some casts in find_fsp_header() - Change HOB access macros to static inline routines - Add comments to mention find_fsp_header() may be called in a stackless environment - Add comments to mention init(¶ms) in fsp_init() cannot be removed Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: crownbay: Add SPI flash support

2014-12-19T00:26:07Z

The Crown Bay board has an SST25VF016B flash connected to the Tunnel Creek processor SPI controller used as the BIOS media where U-Boot is stored. Enable this flash support. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: ich6-gpio: Add Intel Tunnel Creek GPIO support

2014-12-19T00:26:06Z

Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: Add basic support to queensbay platform and crownbay board

2014-12-19T00:26:06Z

Implement minimum required functions for the basic support to queensbay platform and crownbay board. Currently the implementation is to call fsp_init() in the car_init(). We may move that call to cpu_init_f() in the future. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: move arch-specific asmlinkage to

2014-12-15T14:22:53Z

Commit 65dd74a674d6 (x86: ivybridge: Implement SDRAM init) introduced x86-specific asmlinkage into arch/x86/include/asm/config.h. Commit ed0a2fbf14f7 (x86: Add a definition of asmlinkage) added the same macro define again, this time, into include/common.h. (Please do not add arch-specific stuff to include/common.h any more; it is already too cluttered.) The generic asmlinkage is defined in . If you want to override it with an arch-specific one, the best way is to add it to like Linux Kernel. Signed-off-by: Masahiro Yamada Cc: Simon Glass Tested-by: Simon Glass

x86: Support Intel FSP initialization path in start.S

2014-12-14T05:32:05Z

Per Intel FSP architecture specification, FSP provides 3 routines for bootloader to call. The first one is the TempRamInit (aka Cache-As-Ram initialization) and the second one is the FspInit which does the memory bring up (like MRC for other x86 targets) and chipset initialization. Those two routines have to be called before U-Boot jumping to board_init_f in start.S. The FspInit() will return several memory blocks called Hand Off Blocks (HOBs) whose format is described in Platform Initialization (PI) specification (part of the UEFI specication) to the bootloader. Save this HOB address to the U-Boot global data for later use. Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: Add post failure codes for bist and car

2014-12-14T05:32:05Z

Signed-off-by: Bin Meng Acked-by: Simon Glass

x86: queensbay: Adapt FSP support codes

2014-12-14T05:32:05Z

Use inline assembly codes to call FspNotify() to make sure parameters are passed on the stack as required by the FSP calling convention. Signed-off-by: Bin Meng

x86: Initial import from Intel FSP release for Queensbay platform

2014-12-14T05:32:05Z

This is the initial import from Intel FSP release for Queensbay platform (Tunnel Creek processor and Topcliff Platform Controller Hub), which can be downloaded from Intel website. For more details, check http://www.intel.com/fsp. Note: U-Boot coding convention was applied to these codes, so it looks completely different from the original Intel release. Also update FSP support codes license header to use SPDX ID. Signed-off-by: Bin Meng

x86: Add a simple superio driver for SMSC LPC47M

2014-12-14T05:32:05Z

On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8) are provided by a superio chip connected to the LPC bus. We must program the superio chip so that serial ports are available for us. Signed-off-by: Bin Meng Acked-by: Simon Glass