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<title>u-boot.git/arch/x86/include, branch v2016.05</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/include?h=v2016.05</id>
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<updated>2016-03-17T02:27:27Z</updated>
<entry>
<title>x86: Add common SDRAM-init code</title>
<updated>2016-03-17T02:27:27Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-16T13:44:37Z</published>
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<id>urn:sha1:65dd1507e3b744954d43811a1e4d9f194d1bda64</id>
<content type='text'>
The code to call the memory reference code is common to several Intel CPUs.
Add common code for performing this init. Intel calls this 'Pre-EFI-Init'
(PEI), where EFI stands for Extensible Firmware Interface.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Move common PCH code into a common place</title>
<updated>2016-03-17T02:27:27Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-16T13:44:36Z</published>
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<id>urn:sha1:7e4a6ae62c7ee567ae43e94445e561b3ec8343b9</id>
<content type='text'>
The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add a function to set the IOAPIC ID</title>
<updated>2016-03-17T02:27:27Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:07:34Z</published>
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<id>urn:sha1:1cb1611fc6e6223b5281e5e0187855eb0b9f719d</id>
<content type='text'>
Add a function to set the ID in the IOAPIC.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: broadwell: Add support for SDRAM setup</title>
<updated>2016-03-17T02:27:26Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:07:26Z</published>
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<id>urn:sha1:2627c7e2c100c702d540a277aa578176516d3a7c</id>
<content type='text'>
Broadwell uses a binary blob called the memory reference code (MRC) to start
up its SDRAM. This is similar to ivybridge so we can mostly use common code
for running this blob.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: broadwell: Add power-control support</title>
<updated>2016-03-17T02:27:26Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:07:25Z</published>
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<id>urn:sha1:71a8f2080b77591eb14f61aba947aa9e869b847f</id>
<content type='text'>
Broadwell requires quite a bit of power-management setup. Add code to set
this up correctly.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
[squashed in http://patchwork.ozlabs.org/patch/598373/]
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: broadwell: Add an LPC driver</title>
<updated>2016-03-17T02:27:26Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:07:23Z</published>
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<id>urn:sha1:08cb7420a2abe8fb0a99357f2a189c11bfc08d41</id>
<content type='text'>
Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly
uses common code.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: broadwell: Add a pinctrl driver</title>
<updated>2016-03-17T02:27:26Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:07:20Z</published>
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<id>urn:sha1:b24f5c4f27bf6a473fc9a3937a2bbf6ddf0fb104</id>
<content type='text'>
GPIO pins need to be set up on start-up. Add a driver to provide this,
configured from the device tree.

The binding is slightly different from the existing ICH6 binding, since that
is quite verbose. The new binding should be just as extensible.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: broadwell: Add a PCH driver</title>
<updated>2016-03-17T02:27:25Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:07:19Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1e6f4e58862088f31cae350d73f0b1162d0ceb46'/>
<id>urn:sha1:1e6f4e58862088f31cae350d73f0b1162d0ceb46</id>
<content type='text'>
Add a driver for the broadwell low-power platform controller hub.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add basic support for broadwell</title>
<updated>2016-03-17T02:27:25Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:07:18Z</published>
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<id>urn:sha1:2f3f477b77d3a528de41e52a8ba874fd47fb6513</id>
<content type='text'>
This adds the broadwell architecture, with the CPU driver and some useful
header files.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add support for running Intel reference code</title>
<updated>2016-03-17T02:27:25Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:07:16Z</published>
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<id>urn:sha1:0adf8d3548c3fe6f577bb0f2a7acd855dced8a83</id>
<content type='text'>
Intel has invented yet another binary blob which firmware is required to
run. This is run after SDRAM is ready. It is linked to load at a particular
address, typically 0, but is a relocatable ELF so can be moved if required.

Add support for this in the build system. The file should be placed in the
board directory, and called refcode.elf.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
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