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<title>u-boot.git/arch/x86/include, branch v2017.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/include?h=v2017.09</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/x86/include?h=v2017.09'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2017-08-08T08:46:32Z</updated>
<entry>
<title>x86: Remove dead ISA related codes</title>
<updated>2017-08-08T08:46:32Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-08-04T05:52:44Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=091e51d20fcf3d4ec2fdc6e8a1f302be8ad49061'/>
<id>urn:sha1:091e51d20fcf3d4ec2fdc6e8a1f302be8ad49061</id>
<content type='text'>
Neither new design uses ISA bus, nor does any U-Boot codes use these
codes. Remove them.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: kconfig: Select ARCH_EARLY_INIT_R in the platform Kconfig</title>
<updated>2017-08-01T12:17:02Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-07-30T13:23:13Z</published>
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<id>urn:sha1:5d89b37f71ff1833bdd34eeba6dbac6bec1c9fb2</id>
<content type='text'>
This is architecture-dependent early initialization hence should
be put in the platform Kconfig.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Andy Shevchenko &lt;andy.shevchenko@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Make table address selectable</title>
<updated>2017-08-01T12:17:02Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2017-07-28T17:02:15Z</published>
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<id>urn:sha1:c3df28f6e2fc7299883f3340475c532f18754585</id>
<content type='text'>
Some firmwares might have another window for generated tables.

So, introduce two configuration options to select start address and
maximum length for the generated tables.

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: acpi: Export acpi_fill_mcfg() with __weak attribute</title>
<updated>2017-07-30T02:30:25Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2017-07-21T19:32:05Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ace7762b28545e0d2e122d07e81cd4c094fbb298'/>
<id>urn:sha1:ace7762b28545e0d2e122d07e81cd4c094fbb298</id>
<content type='text'>
Some platforms might require different approach when filling memory
mappings configuration table.

Allow them to override the common method.

At the same time export acpi_create_mcfg_mmconfig().

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: acpi: Name fields in FADT in accordance with specification</title>
<updated>2017-07-30T02:30:25Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2017-07-21T19:32:03Z</published>
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<id>urn:sha1:2dcbef6f6c43737b3e9244478c6e768a1e73babf</id>
<content type='text'>
ACPI specification defines FADT fields marked as reserved in U-Boot.

Name these fields in accordance with ACPI specification.

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add Intel Tangier support</title>
<updated>2017-07-30T02:30:25Z</updated>
<author>
<name>Felipe Balbi</name>
<email>felipe.balbi@linux.intel.com</email>
</author>
<published>2017-07-06T11:41:52Z</published>
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<id>urn:sha1:e71de54a4943ac481e8bcdb0a132c52ab90f23fe</id>
<content type='text'>
Add Intel Tangier SoC support.

Intel Tangier SoC is a core part of Intel Merrifield platform. For
example, Intel Edison board is based on such platform.

The patch is based on work done by the following people (in alphabetical
order):
	Aiden Park &lt;aiden.park@intel.com&gt;
	Dukjoon Jeon &lt;dukjoon.jeon@intel.com&gt;
	eric.park &lt;eric.park@intel.com&gt;
	Fabien Chereau &lt;fabien.chereau@intel.com&gt;
	Scott D Phillips &lt;scott.d.phillips@intel.com&gt;
	Sebastien Colleur &lt;sebastienx.colleur@intel.com&gt;
	Steve Sakoman &lt;steve.sakoman@intel.com&gt;
	Vincent Tinelli &lt;vincent.tinelli@intel.com&gt;

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Signed-off-by: Vincent Tinelli &lt;vincent.tinelli@intel.com&gt;
Signed-off-by: Felipe Balbi &lt;felipe.balbi@linux.intel.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>x86: Add dma-mapping.h to architectural code</title>
<updated>2017-07-30T02:30:25Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2017-07-06T11:41:51Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b7026b0c98d2e9f6d190a80c500a0c21a0f3ddc8'/>
<id>urn:sha1:b7026b0c98d2e9f6d190a80c500a0c21a0f3ddc8</id>
<content type='text'>
Some cross-platform drivers rely on this header present.
Make it so for x86.

It's just a copy'n'paste of arch/arm/include/asm/dma-mapping.h.

Suggested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>x86: Don't include asm/u-boot.h in common</title>
<updated>2017-06-05T15:02:35Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-05-17T14:22:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3ff240c92f516841d8aff3b7d9268763711f2afd'/>
<id>urn:sha1:3ff240c92f516841d8aff3b7d9268763711f2afd</id>
<content type='text'>
With a small fixup to u-boot-x86.h, this is not actually needed anywhere,
so drop it.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Make u-boot-x86.h a private header</title>
<updated>2017-06-05T15:02:32Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-05-17T14:22:49Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6862b50f6eebf4379e6d3b74a64378988e8e2961'/>
<id>urn:sha1:6862b50f6eebf4379e6d3b74a64378988e8e2961</id>
<content type='text'>
Rather than including this arch-specific header file in common.h, include
it from within x86's u-boot.h header.

Also drop the comment about something to be fixed. It is not clear what
needs fixing.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: baytrail: Change lpe/lpss-sio/scc FSP properties to integer</title>
<updated>2017-06-05T00:55:22Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-05-31T08:04:15Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f8f291b0962c795fcb025338d5c2284e2357a669'/>
<id>urn:sha1:f8f291b0962c795fcb025338d5c2284e2357a669</id>
<content type='text'>
At present lpe/lpss-sio/scc FSP properties are all boolean, but in
fact for "enable-lpe" it has 3 possible options. This adds macros
for these options and change the property from a boolean type to
an integer type, and change their names to explicitly indicate what
the property is really for.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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