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<title>u-boot.git/arch/x86/include, branch v2018.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/include?h=v2018.01</id>
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<updated>2018-01-08T08:52:25Z</updated>
<entry>
<title>x86: tangier: Add Bluetooth to ACPI table</title>
<updated>2018-01-08T08:52:25Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2018-01-04T16:40:13Z</published>
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<id>urn:sha1:5d8c4ebd95e23a606a40a73920b8d7d096a91d37</id>
<content type='text'>
As defined on reference board followed by Intel Edison a Bluetooth
device is attached to HSU0, i.e. PCI 0000:04.1.

Describe it in ACPI accordingly.

Note, we use BCM2E95 ID here as one most suitable for such device based
on the description in commit message of commit 89ab37b489d1
	("Bluetooth: hci_bcm: Add support for BCM2E95 and BCM2E96")
in the Linux kernel source tree.

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Acked-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: tangier: Use actual GPIO hardware numbers</title>
<updated>2018-01-08T08:52:25Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2018-01-04T16:40:12Z</published>
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<id>urn:sha1:d08953e04596a83076b0f55e7c20b2c2c472e793</id>
<content type='text'>
The recent commit 03c4749dd6c7
  ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation")
in the Linux kernel reveals the issue we have in ACPI tables here,
i.e. we must use hardware numbers for GPIO resources and,
taking into consideration that GPIO and pin control are *different* IPs
on Intel Tangier, we need to supply numbers properly.

Besides that, it improves user experience since the official documentation
for Intel Edison board is referring to GPIO hardware numbering scheme.

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Acked-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: tangier: Use official ACPI HID for FLIS IP</title>
<updated>2017-12-21T01:18:05Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2017-12-12T17:02:42Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1602d215b595b9cf4be460101f5c8892623fe3a0'/>
<id>urn:sha1:1602d215b595b9cf4be460101f5c8892623fe3a0</id>
<content type='text'>
FLIS IP since now gets its own ACPI ID.
Drop PRP0001 workaround in favour of official ACPI HID.

Corresponding kernel commit dabd4bc6de2b

	pinctrl: intel: merrifield: Introduce ACPI device table

in the pin control subsystem tree [1] targeting v4.16.

[1]: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/commit/?h=for-next&amp;id=dabd4bc6de2b

Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>x86: acpi: Put sleepstates.asl to the common place</title>
<updated>2017-10-27T07:13:47Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-10-19T01:21:00Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=411898dc87c09d0cd103a4243c8cb4a72b115c51'/>
<id>urn:sha1:411898dc87c09d0cd103a4243c8cb4a72b115c51</id>
<content type='text'>
The supported sleep states are generic on Intel processors. Move the
ASL definition to the common place.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: baytrail: fsp: Use a function to update the Azalia config pointer</title>
<updated>2017-10-19T03:37:51Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-10-13T08:30:05Z</published>
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<id>urn:sha1:f6859558ca4e18d3a76fafb85924a50026be82fb</id>
<content type='text'>
At present we directly pass the Azalia config pointer to the FSP UPD.
This updates to use a function to do the stuff, like Braswell does.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>x86: fsp: Consolidate Azalia header file</title>
<updated>2017-10-19T03:37:51Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-10-13T08:30:04Z</published>
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<id>urn:sha1:abddcd52ab4979a57dc90ce1b90f8121b43d91b2</id>
<content type='text'>
So far there are two copies of Azalia struct defines with one in
baytrail and the other one in braswell. This consolidates these
two into one, put it in the common place, and remove the prefix
pch_ to these structs to make their names more generic.

This also corrects reset_wait_timer from us to ms.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>x86: tangier: Enable ACPI support for Intel Tangier</title>
<updated>2017-10-07T07:07:59Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2017-10-03T11:55:07Z</published>
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<id>urn:sha1:39665beed6f741fd8ae6ebf23d07fbd546a0d55e</id>
<content type='text'>
Intel Tangier SoC is a part of Intel Merrifield platform which doesn't
utilize ACPI by default. Here is an attempt to unleash ACPI flexibility
power on Intel Merrifield based platforms.

The change brings minimum support of the devices that found on
Intel Merrifield based end user device.

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Use asm-generic/io.h</title>
<updated>2017-10-03T01:52:22Z</updated>
<author>
<name>Paul Burton</name>
<email>paul.burton@imgtec.com</email>
</author>
<published>2017-09-14T22:05:08Z</published>
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<id>urn:sha1:6f01316f3604c3cff635fee03dfe27684f0488c4</id>
<content type='text'>
Convert the x86 architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As the generic implementations are
suitable for x86 this is primarily a matter of moving code.

This has only been build-tested, feedback from architecture maintainers
is welcome.

Signed-off-by: Paul Burton &lt;paul.burton@imgtec.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: x86: Allow TSC timer to be used before DM is ready</title>
<updated>2017-09-16T06:57:44Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-09-06T01:49:46Z</published>
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<id>urn:sha1:2ff50f5fa4009adf5e23a69a4269e6bb054edd79</id>
<content type='text'>
With bootstage we need access to the timer before driver model is set up.
To handle this, put the required state in global_data and provide a new
function to set up the device, separate from the driver's probe() method.

This will be used by the 'early' timer also.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: braswell: Add FSP configuration</title>
<updated>2017-09-16T06:57:44Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-08-16T05:42:00Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fffad9264aa63a2f8da7d15d27d9a7c03a5ff4ec'/>
<id>urn:sha1:fffad9264aa63a2f8da7d15d27d9a7c03a5ff4ec</id>
<content type='text'>
Add FSP related configuration for Braswell.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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