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<title>u-boot.git/arch/x86/include, branch v2020.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/include?h=v2020.01</id>
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<updated>2019-11-02T23:20:28Z</updated>
<entry>
<title>x86: Add a CPU init function for TPL</title>
<updated>2019-11-02T23:20:28Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-10-21T03:37:54Z</published>
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<id>urn:sha1:ece3a4607010226082f2e08afa37419e01ad853f</id>
<content type='text'>
For TPL we only need to set up the features and identify the CPU to a
basic level. Add a function to handle that.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: spl: Support init of a PUNIT</title>
<updated>2019-11-02T23:20:27Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-10-21T03:37:49Z</published>
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<id>urn:sha1:c0e2c81d8e845cd700bb2311514f9d6877f784bb</id>
<content type='text'>
The x86 power unit handles power management. Support initing this device
which is modelled as a new type of system controller since there are no
operations needed.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: timer: Use a separate flag for whether timer is inited</title>
<updated>2019-11-02T23:20:27Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-10-21T03:37:47Z</published>
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<id>urn:sha1:a478a26cd00bbe14d51952b9ae3620415fbdf2b2</id>
<content type='text'>
At present the value of the timer base is used to determine whether the
timer has been set up or not. It is true that the timer is essentially
never exactly 0 when it is read. However 'time 0' may indicate the time
that the machine was reset so it is useful to be able to denote that.

Update the code to use a separate flag instead.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Aiden Park &lt;aiden.park@intel.com&gt;
Reviewed-by: Aiden Park &lt;aiden.park@intel.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add a function to set variable MTRRs</title>
<updated>2019-10-08T05:57:48Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-09-25T14:56:46Z</published>
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<id>urn:sha1:add3f4c9186fbd94b6e89c1d277b544a7a6ad404</id>
<content type='text'>
Normally U-Boot handles MTRRs through an add/commit process which
overwrites all MTRRs. But in very early boot it is not desirable to clear
the existing MTRRs since they may be in use and it can cause a hang.

Add a new mtrr_set_next_var() function which sets up the next available
MTRR to the required region.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
[bmeng: pass 'type' to set_var_mtrr() in mtrr_set_next_var()]
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add new common CPU functions for turbo/burst mode</title>
<updated>2019-10-08T05:57:47Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-09-25T14:56:40Z</published>
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<id>urn:sha1:a27520904f54643c9e55f5672f005a207c911f32</id>
<content type='text'>
Add a few more CPU functions that are common on Intel CPUs. Also add
attribution for the code source.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
[bmeng: add missing MSR_IA32_MISC_ENABLE write back in cpu_set_eist();
        fix 2 typos in cpu_get_burst_mode_state() comments]
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Tidy up some duplicate MSR defines</title>
<updated>2019-10-08T05:57:47Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-09-25T14:56:39Z</published>
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<id>urn:sha1:f6d00da459694a42c1de1e42b159595e2f5ad56f</id>
<content type='text'>
Some MSR registers are defined twice in different parts of the file. Move
them together and remove the duplicates. Also drop some thermal defines
which are not used.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add common functions for TDP and perf control</title>
<updated>2019-10-08T05:57:47Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-09-25T14:56:38Z</published>
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<id>urn:sha1:2f0c2f03e71a68d7e5d8770c10d0154ead6dd104</id>
<content type='text'>
These functions are the same on modern Intel CPUs, so use common code to
set them.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
[bmeng: return false instead of 0 in cpu_ivybridge_config_tdp_levels();
        fix 'muiltiplier' and 'desgn' typos]
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Use a common bus clock for Intel CPUs</title>
<updated>2019-10-08T05:57:47Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-09-25T14:56:37Z</published>
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<id>urn:sha1:55a6b13a75276fbdf7186b34b4ad72238a7ec16b</id>
<content type='text'>
Modern Intel CPUs use a standard bus clock value of 100MHz, so put this in
a common file and tidy up the copies.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add a common function to set CPU thermal target</title>
<updated>2019-10-08T05:57:46Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-09-25T14:56:36Z</published>
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<id>urn:sha1:246ac08b037befab08805750049df75044ab7f6c</id>
<content type='text'>
This code appears in a few places, so move it to a common file.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Use a common definition of MSR_IA32_PERF_CTL</title>
<updated>2019-10-08T05:57:46Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2019-09-25T14:56:35Z</published>
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<id>urn:sha1:e2493a7f5a06854d45175a4aa356ba3a2d810300</id>
<content type='text'>
Remove the duplicate definition as it is not needed.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
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