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<title>u-boot.git/arch/x86/lib/Makefile, branch v2015.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/lib/Makefile?h=v2015.07</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/x86/lib/Makefile?h=v2015.07'/>
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<updated>2015-04-30T03:02:33Z</updated>
<entry>
<title>x86: Add support for the Simple Firmware Interface (SFI)</title>
<updated>2015-04-30T03:02:33Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-04-29T02:25:10Z</published>
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<id>urn:sha1:6388e357254e091fe857493511652a95467b5324</id>
<content type='text'>
This provides a way of passing information to Linux without requiring the
full ACPI horror. Provide a rudimentary implementation sufficient to be
recognised and parsed by Linux.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Support platform PIRQ routing</title>
<updated>2015-04-30T00:51:49Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-04-24T10:10:05Z</published>
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<id>urn:sha1:b5b6b0196017da0c2b4d483a2cd59be7810c1d7a</id>
<content type='text'>
On x86 boards, platform chipset receives up to four different
interrupt signals from PCI devices (INTA/B/C/D), which in turn
will be routed to chipset internal PIRQ lines then routed to
8259 PIC finally if configuring the whole system to work under
the so-called PIC mode (in contrast to symmetric IO mode which
uses IOAPIC).

We add two major APIs to aid this, one for routing PIRQ and the
other one for generating a PIRQ routing table.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Write configuration tables in last_stage_init()</title>
<updated>2015-04-30T00:51:49Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-04-24T10:10:04Z</published>
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<id>urn:sha1:5e2400e8f873a1b7ee840554e4157c5f7900a863</id>
<content type='text'>
We can write the configuration table in last_stage_init() for all x86
boards, but not with coreboot since coreboot already has them.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Remove the old VGA driver</title>
<updated>2015-04-30T00:51:48Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-04-13T11:05:02Z</published>
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<id>urn:sha1:5098d73e86d23d9b76eafcaa6c5bce9e2ef6f6c4</id>
<content type='text'>
CONFIG_VIDEO_VGA is no longer needed thus remove it.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: x86: Add a uclass for an Low Pin Count (LPC) device</title>
<updated>2015-04-18T17:11:14Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-03-26T15:29:28Z</published>
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<id>urn:sha1:a274e9cac55de3c8ca4e877912a260fb646df38d</id>
<content type='text'>
On x86 systems this device is commonly used to provide legacy port access.
It is sort-of a replacement for the old ISA bus.

Add a uclass for this, and allow it to have child devices.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: x86: Add a uclass for a Platform Controller Hub</title>
<updated>2015-04-18T17:11:14Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-03-26T15:29:27Z</published>
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<id>urn:sha1:452f5487536e9d5bf9bb7e515368f6deac7d61f5</id>
<content type='text'>
Add a simple uclass for this chip which is often found in x86 systems
where the CPU is a separate device.

The device can have children, so make it scan the device tree for these.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: x86: pci: Add a PCI driver for driver model</title>
<updated>2015-04-18T17:11:09Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-03-05T19:25:31Z</published>
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<id>urn:sha1:a219daeafef4df1b219db68c80116d82113c82b2</id>
<content type='text'>
Add a simple x86 PCI driver which uses standard functions provided by the
architecture.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Move common FSP code into a common location</title>
<updated>2015-02-06T05:16:43Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-01-28T05:13:36Z</published>
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<id>urn:sha1:1021af4ded2d0961a4ba2ba89851719b098a98b6</id>
<content type='text'>
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add an 'mtrr' command to list and adjust MTRRs</title>
<updated>2015-01-13T15:25:02Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-01-01T23:18:15Z</published>
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<id>urn:sha1:cb3b2e62caa7b87ed727d690c5a8bd1e003ab601</id>
<content type='text'>
It is useful to be able to see the MTRR setup in U-Boot. Add a command
to list the state of the variable MTRR registers and allow them to be
changed.

Update the documentation to list some of the available commands.

This does not support fixed MTRRs as yet.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add a simple command to show FSP HOB information</title>
<updated>2014-12-14T05:32:06Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2014-12-12T13:05:32Z</published>
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<id>urn:sha1:ba7b38a5295d9bad1a95f53f0a3ade20441a3831</id>
<content type='text'>
FSP builds a series of data structures called the Hand-Off-Blocks
(HOBs) as it progresses through initializing the silicon. These data
structures conform to the HOB format as described in the Platform
Initialization (PI) specification Volume 3 Shared Architectual
Elements specification, which is part of the UEFI specification.

Create a simple command to parse the HOB list to display the HOB
address, type and length in bytes.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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