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<title>u-boot.git/arch/x86/lib/Makefile, branch v2016.03</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/lib/Makefile?h=v2016.03</id>
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<updated>2016-02-05T04:47:24Z</updated>
<entry>
<title>x86: Drop pci_type1.c and DEFINE_PCI_DEVICE_TABLE</title>
<updated>2016-02-05T04:47:24Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-02T13:58:09Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5c884420a5752163ce738701701ae1874d8f466d'/>
<id>urn:sha1:5c884420a5752163ce738701701ae1874d8f466d</id>
<content type='text'>
Now that we have converted all x86 codes to DM PCI, drop pci_type1.c
which is only built for legacy PCI. Also per checkpatch.pl warning,
DEFINE_PCI_DEVICE_TABLE is now deprecated so drop that too.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: qemu: add the ability to load and link ACPI tables from QEMU</title>
<updated>2016-01-28T05:53:30Z</updated>
<author>
<name>Miao Yan</name>
<email>yanmiaobest@gmail.com</email>
</author>
<published>2016-01-20T09:57:06Z</published>
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<id>urn:sha1:fa287b158099b5b2159ecbbcc4acb2d5dc6714cf</id>
<content type='text'>
This patch adds the ability to load and link ACPI tables provided by QEMU.
QEMU tells guests how to load and patch ACPI tables through its fw_cfg
interface, by adding a firmware file 'etc/table-loader'. Guests are
supposed to parse this file and execute corresponding QEMU commands.

Signed-off-by: Miao Yan &lt;yanmiaobest@gmail.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>dm: x86: Add a northbridge uclass</title>
<updated>2016-01-24T04:08:16Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-17T23:11:14Z</published>
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<id>urn:sha1:5544757ce97c72119359eb47aa57d28e46fdf405</id>
<content type='text'>
Add a uclass for the northbridge / SDRAM controller found on some older
Intel chipsets.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>dm: Expand the uclass for Platform Controller Hubs (PCH)</title>
<updated>2016-01-24T04:07:17Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-19T03:19:17Z</published>
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<id>urn:sha1:ca831f4933dc68d9ed1b6399cbda90068c520005</id>
<content type='text'>
A Platform Controller Hub is an Intel concept - it is like the peripherals
on an SoC and is often in a separate chip from the CPU. The chip is typically
found on the first PCI bus and integrates multiple devices.

We have a very simple uclass to support PCHs. Add a few operations, such as
setting up the devices on the PCH and finding the SPI controller base
address. Also move it into drivers/pch/ since we will be adding a few PCH
drivers.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: tsc: Move tsc_timer.c to drivers/timer</title>
<updated>2015-12-01T13:26:35Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-11-13T08:11:24Z</published>
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<id>urn:sha1:7030f27ef3da9f911299592751574044f86305f0</id>
<content type='text'>
To group all dm timer drivers together, move tsc timer to
drivers/timer directory.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Rename pcat_ to i8254 and i8259 accordingly</title>
<updated>2015-11-13T14:46:18Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-10-23T02:13:30Z</published>
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<id>urn:sha1:da3fe247591e17dead357f05f69124c54aa13a01</id>
<content type='text'>
Rename pcat_timer.c to i8254.c and pcat_interrupts.c to i8259.c,
to match their header file names (i8254.h and i8259.h).

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Move mrccache.[c|h] to a common place</title>
<updated>2015-10-21T13:46:26Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-10-12T04:37:36Z</published>
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<id>urn:sha1:f6220f1a86109f88950fd42e3af54314de24365a</id>
<content type='text'>
mrccache implementation can be common for all boards. Move it
from ivybridge cpu directory to the common lib directory.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: fsp: Make hob command a sub-command to fsp</title>
<updated>2015-10-21T13:46:26Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-10-10T08:47:58Z</published>
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<id>urn:sha1:62716ebb751dbe7346ff52b17be867505d959bcc</id>
<content type='text'>
Introduce a new fsp command and make the existing hob command a
sub-command to fsp for future extension. Also move cmd_hob.c to
the dedicated fsp sub-directory in arch/x86/lib.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Add SMBIOS table support</title>
<updated>2015-10-21T13:46:26Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-10-12T12:23:41Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=721e992a8af5e80b2a95a0bc92c9880f2056190b'/>
<id>urn:sha1:721e992a8af5e80b2a95a0bc92c9880f2056190b</id>
<content type='text'>
System Management BIOS (SMBIOS) is a specification for how
motherboard and system vendors present management information
about their products in a standard format by extending the BIOS
interface on Intel architecture systems. As of today the latest
spec is 3.0 and can be downloaded from DMTF website. This commit
adds a simple and minimum required implementation.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Move install_e820_map() out of zimage.c</title>
<updated>2015-10-21T13:46:25Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-10-08T03:19:10Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=59ec719df62bcb397066aeee66fdbd8f042ca3c7'/>
<id>urn:sha1:59ec719df62bcb397066aeee66fdbd8f042ca3c7</id>
<content type='text'>
install_e820_map() has nothing to do with zimage related codes.
Move it to a dedicated place.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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