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<title>u-boot.git/arch/x86/lib/init_helpers.c, branch v2016.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/lib/init_helpers.c?h=v2016.07</id>
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<updated>2015-08-26T14:54:07Z</updated>
<entry>
<title>x86: Remove calculate_relocation_address()</title>
<updated>2015-08-26T14:54:07Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-08-13T07:29:10Z</published>
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<id>urn:sha1:c17ca6b5cd7158b63a78c4944c732c49dce8454f</id>
<content type='text'>
Now that we have generic routine to calculate relocation address,
remove the x86 specific one which is now only used by coreboot.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>dm: x86: spi: Convert ICH SPI driver to driver model</title>
<updated>2015-04-18T17:11:14Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-03-26T15:29:26Z</published>
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<id>urn:sha1:ba4575626eddef71b5a8dc26dc4b267918b9438c</id>
<content type='text'>
Convert this driver over to use driver model. Since all x86 platforms use
it, move x86 to use driver model for SPI and SPI flash. Adjust all dependent
code and remove the old x86 spi_init() function.

Note that this does not make full use of the new PCI uclass as yet. We still
scan the bus looking for the device. It should move to finding its details
in the device tree.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Test mtrr support flag before accessing mtrr msr</title>
<updated>2015-01-24T00:24:55Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-01-22T03:29:41Z</published>
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<id>urn:sha1:3b621ccabdccb34891bb58865a9654a09c2b7279</id>
<content type='text'>
On some x86 processors (like Intel Quark) the MTRR registers are not
supported. This is reflected by the CPUID (EAX 01H) result EDX[12].
Accessing the MTRR registers on such processors will cause #GP so we
must test the support flag before accessing MTRR MSRs.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Commit the current MTRRs before relocation</title>
<updated>2015-01-13T15:25:01Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-01-01T23:18:11Z</published>
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<id>urn:sha1:db55bd7dad9a2c30c8da884bf20273945e240430</id>
<content type='text'>
Once we stop running from ROM we should set up the MTTRs to speed up
execution. This is only needed for platforms that don't have an FSP.
Also in the Coreboot case, the MTRRs are set up for us.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Remove unnecessary find_fdt(), prepare_fdt() functions</title>
<updated>2014-11-21T06:24:12Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-11-11T01:00:25Z</published>
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<id>urn:sha1:003504b6fe2296f581191b77fd2f1e98c4f4720c</id>
<content type='text'>
These are no-longer needed so drop them.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>dts: re-write dts/Makefile more simply with Kbuild</title>
<updated>2014-02-19T16:10:05Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.m@jp.panasonic.com</email>
</author>
<published>2014-02-05T02:28:25Z</published>
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<id>urn:sha1:6ab6b2afa091dbceb37719b8a81637a00834be19</id>
<content type='text'>
Useful rules in scripts/Makefile.lib allows us to easily
generate a device tree blob and wrap it in assembly code.

We do not need to parse a linker script to get output format and arch.

This commit deletes ./u-boot.dtb since it is a copy of dts/dt.dtb.

Signed-off-by: Masahiro Yamada &lt;yamada.m@jp.panasonic.com&gt;
</content>
</entry>
<entry>
<title>Add GPL-2.0+ SPDX-License-Identifier to source files</title>
<updated>2013-07-24T13:44:38Z</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2013-07-08T07:37:19Z</published>
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<id>urn:sha1:1a4596601fd395f3afb8f82f3f840c5e00bdd57a</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</content>
</entry>
<entry>
<title>x86: Remove legacy board init code</title>
<updated>2013-05-13T20:33:20Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-04-17T16:13:32Z</published>
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<id>urn:sha1:fa790fa0a91b9d029ec6fdac791066bc5d16b862</id>
<content type='text'>
Since we use CONFIG_SYS_GENERIC_BOARD on x86, we don't need this anymore.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Graeme Russ &lt;graeme.russ@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Use sections header to obtain link symbols</title>
<updated>2013-03-15T20:14:00Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-03-05T14:39:54Z</published>
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<id>urn:sha1:86cfb6bdecc3a312a939bbd89560f500f45193c3</id>
<content type='text'>
These are defined in asm-generic/sections.h, so remove them from
architecture-specific files.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Introduce generic pre-relocation board_f.c</title>
<updated>2013-03-15T20:13:59Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-03-11T06:49:53Z</published>
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<id>urn:sha1:1938f4a5b62fc03c52b47697a89b2bb47b77c90c</id>
<content type='text'>
This file handles common pre-relocation init for boards which use
the generic framework.

It starts up the console, DRAM, performs relocation and then jumps
to post-relocation init.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Wolfgang Denk &lt;wd@denx.de&gt;
Acked-by: Wolfgang Denk &lt;wd@denx.de&gt;
</content>
</entry>
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