u-boot.git/arch/x86/lib/tsc_timer.c, branch master

x86: tsc: Move tsc_timer.c to drivers/timer

2015-12-01T13:26:35+00:00

To group all dm timer drivers together, move tsc timer to
drivers/timer directory.

Signed-off-by: Bin Meng 
Acked-by: Simon Glass

x86: tsc: Remove legacy timer codes

2015-12-01T13:26:35+00:00

Now that we have converted all x86 boards to use driver model timer,
remove these legacy timer codes in the tsc driver.

Note this also removes the TSC_CALIBRATION_BYPASS Kconfig option,
as it is not needed with driver model.

Signed-off-by: Bin Meng 
Acked-by: Simon Glass

x86: tsc: Add driver model timer support

2015-12-01T13:23:51+00:00

This adds driver model timer support to x86 tsc timer driver.

Signed-off-by: Bin Meng 
Acked-by: Simon Glass

x86: tsc: Use notrace from

2015-12-01T13:23:51+00:00

Replace __attribute__((no_instrument_function)) with notrace from
.

Signed-off-by: Bin Meng 
Acked-by: Simon Glass

x86: Rename pcat_ to i8254 and i8259 accordingly

2015-11-13T14:46:18+00:00

Rename pcat_timer.c to i8254.c and pcat_interrupts.c to i8259.c,
to match their header file names (i8254.h and i8259.h).

Signed-off-by: Bin Meng 
Acked-by: Simon Glass

x86: Add a 'pause' instruction in __udelay() for QEMU target

2015-08-05T14:42:38+00:00

When running SMP configuration on QEMU (tcg mode, no kvm), there is
a busy loop in start_aps(), calling udelay(), that waits for APs to
show up online. However, there is a chance that VCPU1 will be timeout
waiting, IOW the secondary VCPUs haven't started their execution yet.

This patch adds a 'pause' instruction in __udelay() only for QEMU
target, to give other VCPUs a chance to run. When QEMU sees the
'pause' instruction, it will yeild the execution to other CPUs.

Signed-off-by: Miao Yan 
Signed-off-by: Bin Meng 
Acked-by: Simon Glass 
Tested-by: Simon Glass

x86: Allow a hardcoded TSC frequency provided by Kconfig

2015-01-13T15:25:02+00:00

By default U-Boot automatically calibrates TSC running frequency via
MSR and PIT. The calibration may not work on every x86 processor, so
a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
allow bypassing the calibration and assign a hardcoded TSC frequency
CONFIG_TSC_FREQ_IN_MHZ.

Normally the bypass should be turned on in a simulation environment
like qemu.

Signed-off-by: Bin Meng 
Acked-by: Simon Glass

x86: Allow timer calibration to work on ivybridge

2014-11-21T06:24:12+00:00

Unfortunately MSR_FSB_FREQ is not available on this CPU, and the PIT method
seems to take up to 50ms which is much too long.

For this CPU we know the frequency, so add another special case for now.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng

x86: Save TSC frequency in the global data

2014-11-21T06:24:10+00:00

Return the saved TSC frequency in get_tbclk_mhz().

Signed-off-by: Bin Meng 
Acked-by: Simon Glass 
Tested-by: Simon Glass

x86: Add quick TSC calibration via PIT

2014-11-21T06:24:10+00:00

Use the same way that Linux does for quick TSC calibration via PIT
when calibration via MSR fails.

Signed-off-by: Bin Meng 
Acked-by: Simon Glass