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<title>u-boot.git/arch/x86/lib, branch v2015.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/lib?h=v2015.07</id>
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<updated>2015-06-04T08:39:39Z</updated>
<entry>
<title>x86: fsp_support: Correct high mem comment typo</title>
<updated>2015-06-04T08:39:39Z</updated>
<author>
<name>Andrew Bradford</name>
<email>andrew.bradford@kodakalaris.com</email>
</author>
<published>2015-05-22T19:11:23Z</published>
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<id>urn:sha1:1dc03c2639e6768c46c1db9ddbd2177e6962408e</id>
<content type='text'>
High mem starts at 4 GiB.

Signed-off-by: Andrew Bradford &lt;andrew.bradford@kodakalaris.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Add support for the Simple Firmware Interface (SFI)</title>
<updated>2015-04-30T03:02:33Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-04-29T02:25:10Z</published>
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<id>urn:sha1:6388e357254e091fe857493511652a95467b5324</id>
<content type='text'>
This provides a way of passing information to Linux without requiring the
full ACPI horror. Provide a rudimentary implementation sufficient to be
recognised and parsed by Linux.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: fsp: Use reset_cpu()</title>
<updated>2015-04-30T03:02:32Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-04-29T02:11:32Z</published>
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<id>urn:sha1:410b10f1e329ae49340500e0fbc4ac011ba40001</id>
<content type='text'>
Now that reset_cpu() functions correctly, use it instead of directly
accessing the port on boards that use a Firmware Support Package (FSP).

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Correct the typo in write_tables()</title>
<updated>2015-04-30T00:51:50Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-04-28T10:37:03Z</published>
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<id>urn:sha1:cc4c8aca1de4a0a6ef81460217f64c4b76de5340</id>
<content type='text'>
It should be #ifdef instead of #if.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Check PIRQ routing table sanity in the F segment</title>
<updated>2015-04-30T00:51:50Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-04-27T06:16:01Z</published>
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<id>urn:sha1:283a08e52a0d3f5fe8ac3139c632f32a03fc44f0</id>
<content type='text'>
Previously the PIRQ routing table sanity check was performed against
the original table provided by the platform codes. Now we switch to
check its sanity on the final table in the F segment as this one is
the one seen by the OS.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Support platform PIRQ routing</title>
<updated>2015-04-30T00:51:49Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-04-24T10:10:05Z</published>
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<id>urn:sha1:b5b6b0196017da0c2b4d483a2cd59be7810c1d7a</id>
<content type='text'>
On x86 boards, platform chipset receives up to four different
interrupt signals from PCI devices (INTA/B/C/D), which in turn
will be routed to chipset internal PIRQ lines then routed to
8259 PIC finally if configuring the whole system to work under
the so-called PIC mode (in contrast to symmetric IO mode which
uses IOAPIC).

We add two major APIs to aid this, one for routing PIRQ and the
other one for generating a PIRQ routing table.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Write configuration tables in last_stage_init()</title>
<updated>2015-04-30T00:51:49Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-04-24T10:10:04Z</published>
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<id>urn:sha1:5e2400e8f873a1b7ee840554e4157c5f7900a863</id>
<content type='text'>
We can write the configuration table in last_stage_init() for all x86
boards, but not with coreboot since coreboot already has them.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Install a default e820 table in the __weak install_e820_map()</title>
<updated>2015-04-30T00:51:49Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-04-21T04:21:36Z</published>
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<id>urn:sha1:54c6001bbac1cb3b6b85605d115e5f73ef1ab198</id>
<content type='text'>
Create a default e820 table with 3 entries which is enough to boot
a Linux kernel.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Remove the old VGA driver</title>
<updated>2015-04-30T00:51:48Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-04-13T11:05:02Z</published>
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<id>urn:sha1:5098d73e86d23d9b76eafcaa6c5bce9e2ef6f6c4</id>
<content type='text'>
CONFIG_VIDEO_VGA is no longer needed thus remove it.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: x86: Add a uclass for an Low Pin Count (LPC) device</title>
<updated>2015-04-18T17:11:14Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-03-26T15:29:28Z</published>
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<id>urn:sha1:a274e9cac55de3c8ca4e877912a260fb646df38d</id>
<content type='text'>
On x86 systems this device is commonly used to provide legacy port access.
It is sort-of a replacement for the old ISA bus.

Add a uclass for this, and allow it to have child devices.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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