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<title>u-boot.git/arch/x86/lib, branch v2016.03</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86/lib?h=v2016.03</id>
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<updated>2016-02-21T05:42:52Z</updated>
<entry>
<title>x86: fsp: Make sure HOB list is not overwritten by U-Boot</title>
<updated>2016-02-21T05:42:52Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-17T08:16:23Z</published>
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<id>urn:sha1:dc5be508b065ff305cef451ac1aed7465603db02</id>
<content type='text'>
Intel IvyBridge FSP seems to be buggy that it does not report memory
used by FSP itself as reserved in the resource descriptor HOB. The
FSP specification does not describe how resource descriptor HOBs are
generated by the FSP to describe what memory regions. It looks newer
FSPs like Queensbay and BayTrail do not have such issue. This causes
U-Boot relocation overwrites the important boot service data which is
used by FSP, and the subsequent call to fsp_notify() will fail.

To resolve this, we find out the lowest memory base address allocated
by FSP for the boot service data when walking through the HOB list in
fsp_get_usable_lowmem_top(). Check whether the memory top address is
below the FSP HOB list, and if not, use the lowest memory base address
allocated by FSP as the memory top address.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging</title>
<updated>2016-02-08T14:48:04Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-02-08T14:48:04Z</published>
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<id>urn:sha1:57dc53a72460e8e301fa1cc7951b41db8e731485</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Use correct spelling of "U-Boot"</title>
<updated>2016-02-06T11:00:59Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-06T03:30:11Z</published>
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<id>urn:sha1:a187559e3d586891c917279044c5386d1b2adc6e</id>
<content type='text'>
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Heiko Schocher &lt;hs@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>x86: Drop pci_type1.c and DEFINE_PCI_DEVICE_TABLE</title>
<updated>2016-02-05T04:47:24Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-02T13:58:09Z</published>
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<id>urn:sha1:5c884420a5752163ce738701701ae1874d8f466d</id>
<content type='text'>
Now that we have converted all x86 codes to DM PCI, drop pci_type1.c
which is only built for legacy PCI. Also per checkpatch.pl warning,
DEFINE_PCI_DEVICE_TABLE is now deprecated so drop that too.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: irq: Move irq_router to a per driver priv</title>
<updated>2016-02-05T04:47:22Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-01T09:40:51Z</published>
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<id>urn:sha1:b46c2088da17b8f9210bf0860af88ec533435af9</id>
<content type='text'>
At present irq_router is declared as a static struct irq_router in
arch/x86/cpu/irq.c. Since it's a driver control block, it makes sense
to move it to a per driver priv. Adjust existing APIs to accept an
additional parameter of irq_router's udevice.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: qemu: add the ability to load and link ACPI tables from QEMU</title>
<updated>2016-01-28T05:53:30Z</updated>
<author>
<name>Miao Yan</name>
<email>yanmiaobest@gmail.com</email>
</author>
<published>2016-01-20T09:57:06Z</published>
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<id>urn:sha1:fa287b158099b5b2159ecbbcc4acb2d5dc6714cf</id>
<content type='text'>
This patch adds the ability to load and link ACPI tables provided by QEMU.
QEMU tells guests how to load and patch ACPI tables through its fw_cfg
interface, by adding a firmware file 'etc/table-loader'. Guests are
supposed to parse this file and execute corresponding QEMU commands.

Signed-off-by: Miao Yan &lt;yanmiaobest@gmail.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: baytrail: Add option to disable the internal UART to setup_early_uart()</title>
<updated>2016-01-28T05:53:30Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2016-01-19T13:24:12Z</published>
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<id>urn:sha1:d521197d69c0fe85afdd75c537783adf95905ede</id>
<content type='text'>
This patch adds a parameter to the function setup_early_uart() to either
enable or disable the internal BayTrail legacy UART. Since the name
setup_early_uart() does not match its functionality any more, lets
rename it to setup_internal_uart() as well in this patch.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Don't show an error when the MRC cache is up to date</title>
<updated>2016-01-24T04:08:17Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-17T23:11:29Z</published>
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<id>urn:sha1:8b674418e0250aae9748d9b53fe4c9d9607b7e36</id>
<content type='text'>
When the final MRC cache record is the same as the one we want to write, we
skip writing since there is no point. This is normal behaviour.

Avoiding printing an error when this happens.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>dm: x86: Add a northbridge uclass</title>
<updated>2016-01-24T04:08:16Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-17T23:11:14Z</published>
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<id>urn:sha1:5544757ce97c72119359eb47aa57d28e46fdf405</id>
<content type='text'>
Add a uclass for the northbridge / SDRAM controller found on some older
Intel chipsets.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Use the IRQ device when setting up the mptable</title>
<updated>2016-01-24T04:07:18Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-20T04:32:28Z</published>
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<id>urn:sha1:b565d66d2ca1748c9b0520fa4ba46b4a5dfa5468</id>
<content type='text'>
Instead of searching for the device tree node, use the IRQ device which has
a record of it.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
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