u-boot.git/arch/x86/lib, branch v2016.05

x86: Add an ICH6 pin configuration driver

2016-03-17T02:27:25Z

Add a driver which sets up the pin configuration on x86 devices with an ICH6 (or later) Platform Controller Hub. The driver is not in the pinctrl uclass due to some oddities of the way x86 devices work: - The GPIO controller is not present in I/O space until it is set up - This is done by writing a register in the PCH - The PCH has a driver which itself uses PCI, another driver - The pinctrl uclass requires that a pinctrl device be available before any other device can be probed It would be possible to work around the limitations by: - Hard-coding the GPIO address rather than reading it from the PCH - Using special x86 PCI access to set the GPIO address in the PCH However it is not clear that this is better, since the pin configuration driver does not actually provide normal pin configuration services - it simply sets up all the pins statically when probed. While this remains the case, it seems better to use a syscon uclass instead. This can be probed whenever it is needed, without any limitations. Also add an 'invert' property to support inverting the input. Signed-off-by: Simon Glass Reviewed-by: Bin Meng

x86: Update microcode for secondary CPUs

2016-03-17T02:27:25Z

Each CPU needs to have its microcode loaded. Add support for this so that all CPUs will have the same version. Signed-off-by: Simon Glass Reviewed-by: Bin Meng

x86: Support booting SeaBIOS

2016-03-17T02:27:22Z

SeaBIOS is an open source implementation of a 16-bit x86 BIOS. It can run in an emulator or natively on x86 hardware with the use of coreboot. With SeaBIOS's help, we can boot some OSes that require 16-bit BIOS services like Windows/DOS. As U-Boot, we have to manually create a table where SeaBIOS gets system information (eg: E820) from. The table unfortunately has to follow the coreboot table format as SeaBIOS currently supports booting as a coreboot payload. Signed-off-by: Bin Meng Reviewed-by: Simon Glass

x86: Implement functions for writing coreboot table

2016-03-17T02:27:22Z

To prepare generating coreboot table from U-Boot, implement functions to handle the writing. Signed-off-by: Bin Meng Reviewed-by: Simon Glass

x86: Support writing configuration tables in high area

2016-03-17T02:27:22Z

For those secondary bootloaders like SeaBIOS who want to live in the F segment, which conflicts the configuration table address, now we allow write_tables() to write the configuration tables in high area (malloc'ed memory). Signed-off-by: Bin Meng Reviewed-by: Simon Glass

x86: Simplify codes in write_tables()

2016-03-17T02:27:22Z

Given all table write routines have the same signature, we can simplify the codes by using a function table. Signed-off-by: Bin Meng Reviewed-by: Simon Glass

x86: Change write_acpi_tables() signature a little bit

2016-03-17T02:27:22Z

Change the parameter and return value of write_acpi_tables() to u32 to conform with other table write routines. Signed-off-by: Bin Meng Reviewed-by: Simon Glass

x86: Use a macro for ROM table alignment

2016-03-17T02:27:22Z

Define ROM_TABLE_ALIGN instead of using 1024 directly. Signed-off-by: Bin Meng Reviewed-by: Simon Glass

x86: Change to use start/end address pair in write_tables()

2016-03-17T02:27:22Z

Add a new variable rom_table_start and pass it to ROM table write routines. This reads better than previous single rom_table_end. Signed-off-by: Bin Meng Reviewed-by: Simon Glass

dm: Use uclass_first_device_err() where it is useful

2016-03-14T21:34:50Z

Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass