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<title>u-boot.git/arch/x86, branch v2015.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86?h=v2015.01</id>
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<updated>2014-12-19T00:26:08Z</updated>
<entry>
<title>x86: Clean up the FSP support codes</title>
<updated>2014-12-19T00:26:08Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2014-12-17T07:50:49Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=255fd5caa5dda7f1028843753562eff58f3855bc'/>
<id>urn:sha1:255fd5caa5dda7f1028843753562eff58f3855bc</id>
<content type='text'>
This is the follow-on patch to clean up the FSP support codes:

- Remove the _t suffix on the structures defines
- Use __packed for structure defines
- Use U-Boot's assert()
- Use standard bool true/false
- Remove read_unaligned64()
- Use memcmp() in the compare_guid()
- Remove the cast in the memset() call
- Replace some magic numbers with macros
- Use panic() when no valid FSP image header is found
- Change some FSP utility routines to use an fsp_ prefix
- Add comment blocks for asm_continuation and fsp_init_done
- Remove some casts in find_fsp_header()
- Change HOB access macros to static inline routines
- Add comments to mention find_fsp_header() may be called in a
  stackless environment
- Add comments to mention init(&amp;params) in fsp_init() cannot
  be removed

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Rename coreboot-serial to x86-serial</title>
<updated>2014-12-19T00:26:08Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2014-12-17T07:50:47Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=41702bac01c585cc11fa5dd1f38dea1e5a7c642d'/>
<id>urn:sha1:41702bac01c585cc11fa5dd1f38dea1e5a7c642d</id>
<content type='text'>
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: crownbay: Add SDHCI support</title>
<updated>2014-12-19T00:26:08Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2014-12-17T07:50:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=aada6276c68daf0229442aa8bf6e60aae4c4fd0d'/>
<id>urn:sha1:aada6276c68daf0229442aa8bf6e60aae4c4fd0d</id>
<content type='text'>
There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: crownbay: Add SPI flash support</title>
<updated>2014-12-19T00:26:07Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2014-12-17T07:50:44Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=adfe3b247a7a281931f0fd865e9d00600e9dd384'/>
<id>urn:sha1:adfe3b247a7a281931f0fd865e9d00600e9dd384</id>
<content type='text'>
The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Use consistent name XXX_ADDR for binary blob flash address</title>
<updated>2014-12-19T00:26:07Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2014-12-17T07:50:42Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8c5224c9f5c8a24ff5153f018e10a3ac4da5783a'/>
<id>urn:sha1:8c5224c9f5c8a24ff5153f018e10a3ac4da5783a</id>
<content type='text'>
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Add queensbay and crownbay Kconfig files</title>
<updated>2014-12-19T00:26:06Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2014-12-17T07:50:40Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=58f542de30e3bae9845726af36e0e25b5b458e8c'/>
<id>urn:sha1:58f542de30e3bae9845726af36e0e25b5b458e8c</id>
<content type='text'>
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Enable the queensbay cpu directory build</title>
<updated>2014-12-19T00:26:06Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2014-12-17T07:50:39Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=240a79d95cc13bdeb02af5cc3451735df24715aa'/>
<id>urn:sha1:240a79d95cc13bdeb02af5cc3451735df24715aa</id>
<content type='text'>
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: ich6-gpio: Add Intel Tunnel Creek GPIO support</title>
<updated>2014-12-19T00:26:06Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2014-12-17T07:50:38Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b71eec3129c2626bfb1e98141b317d958e3cf384'/>
<id>urn:sha1:b71eec3129c2626bfb1e98141b317d958e3cf384</id>
<content type='text'>
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.

Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Convert microcode format to device-tree-only</title>
<updated>2014-12-19T00:26:06Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-12-17T07:50:37Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0f61de8d9dba4ebfc4ea4b2da7f91adc937b3875'/>
<id>urn:sha1:0f61de8d9dba4ebfc4ea4b2da7f91adc937b3875</id>
<content type='text'>
To avoid having two microcode formats, adjust the build system to support
obtaining the microcode from the device tree, even in the case where it
must be made available before the device tree can be accessed.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add basic support to queensbay platform and crownbay board</title>
<updated>2014-12-19T00:26:06Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2014-12-17T07:50:36Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b2e02d28653edac48d6def9791f2fa0ebc491498'/>
<id>urn:sha1:b2e02d28653edac48d6def9791f2fa0ebc491498</id>
<content type='text'>
Implement minimum required functions for the basic support to
queensbay platform and crownbay board.

Currently the implementation is to call fsp_init() in the car_init().
We may move that call to cpu_init_f() in the future.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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