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<title>u-boot.git/arch/x86, branch v2015.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86?h=v2015.07</id>
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<updated>2015-06-26T02:17:55Z</updated>
<entry>
<title>Move default y configs out of arch/board Kconfig</title>
<updated>2015-06-26T02:17:55Z</updated>
<author>
<name>Joe Hershberger</name>
<email>joe.hershberger@ni.com</email>
</author>
<published>2015-06-22T21:15:29Z</published>
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<id>urn:sha1:c9bb942e2f91d9f8e5f25ed1961eba2d64f65b8d</id>
<content type='text'>
Some archs/boards specify their own default by pre-defining the config
which causes the Kconfig system to mix up the order of the configs in
the defconfigs... This will cause merge pain if allowed to proliferate.

Remove the configs that behave this way from the archs.

A few configs still remain, but that is because they only exist as
defaults and do not have a proper Kconfig entry. Those appear to be:

SPIFLASH
DISPLAY_BOARDINFO

Signed-off-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
[trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates,
drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>x86: gpio: add pinctrl support from the device tree</title>
<updated>2015-06-04T09:32:08Z</updated>
<author>
<name>Gabriel Huau</name>
<email>contact@huau-gabriel.fr</email>
</author>
<published>2015-05-26T05:27:37Z</published>
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<id>urn:sha1:5318f18d2c002f505054b90bb95ba7c53532eedf</id>
<content type='text'>
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.

Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975
Signed-off-by: Gabriel Huau &lt;contact@huau-gabriel.fr&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: baytrail: pci region 3 is not always mapped to end of ram</title>
<updated>2015-06-04T09:03:18Z</updated>
<author>
<name>Andrew Bradford</name>
<email>andrew.bradford@kodakalaris.com</email>
</author>
<published>2015-06-03T16:37:39Z</published>
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<id>urn:sha1:afbbd413a3ef8a45155fcd083814ba645b09fcc7</id>
<content type='text'>
Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF
and additional SDRAM is mapped from 0x100000000 and up.  There is a
physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses.
Because of this, PCI region 3 should only try to use up to the amount of
SDRAM or 0x80000000, which ever is less.

Signed-off-by: Andrew Bradford &lt;andrew.bradford@kodakalaris.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: qemu: Implement PIRQ routing</title>
<updated>2015-06-04T09:03:18Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-06-03T01:20:06Z</published>
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<id>urn:sha1:5c564226fc8948e435edea8eb8c5c4afbc5edef1</id>
<content type='text'>
Support QEMU PIRQ routing via device tree on both i440fx and q35
platforms. With this commit, Linux booting on QEMU from U-Boot
has working ATA/SATA, USB and ethernet.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Control I/O port 0xb2 writing via device tree</title>
<updated>2015-06-04T09:03:18Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-06-03T01:20:05Z</published>
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<id>urn:sha1:f2653e8dd92229328480da35c26e6f9fbfec4381</id>
<content type='text'>
Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
U-Boot to hang on QEMU q35 target. We introduce a config option in the
device tree "u-boot,no-apm-finalize" under /config node if we don't want
to do that.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: qemu: Create separate i440fx and q35 device trees</title>
<updated>2015-06-04T09:03:18Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-06-03T01:20:04Z</published>
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<id>urn:sha1:683b09d7837a71fb4c5dd53919c6afa4d800e60e</id>
<content type='text'>
Although the two qemu-x86 targets (i440fx and q35) share a lot in
common, they still have something that cannot easily handled in one
single device tree). Split to create two dedicated device tree files
and make the i440fx be the default build target.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: coreboot: Fix cosmetic issues</title>
<updated>2015-06-04T09:03:17Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-06-03T01:20:02Z</published>
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<id>urn:sha1:65cdd9be3e0fe79909962bba9bedf7967d44d60b</id>
<content type='text'>
Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: kconfig: Make FSP_TEMP_RAM_ADDR depend on HAVE_FSP</title>
<updated>2015-06-04T09:03:17Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-06-01T13:07:23Z</published>
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<id>urn:sha1:d04e30b839f3a60b72fda7021eaf2f94b185d756</id>
<content type='text'>
FSP_TEMP_RAM_ADDR should only be visible when HAVE_FSP is on.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: qemu: Adjust VGA initialization</title>
<updated>2015-06-04T08:39:40Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-05-25T14:36:27Z</published>
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<id>urn:sha1:4be2f42bbc8171eae930db37f370f10779c5b02c</id>
<content type='text'>
As VGA option rom needs to run at C segment, although QEMU PAM emulation
seems to only guard E/F segments, for correctness, move VGA initialization
after PAM decode C/D/E/F segments.

Also since we already tested QEMU targets to differentiate I440FX and Q35
platforms, change to locate the VGA device via hardcoded b.d.f instead of
dynamic search for its vendor id &amp; device id pair.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: qemu: Enable legacy IDE I/O ports decode</title>
<updated>2015-06-04T08:39:39Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-05-25T14:36:26Z</published>
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<id>urn:sha1:0fcb7acf6748d2ee0b7abfd75e074840be6b7e0e</id>
<content type='text'>
QEMU always decode legacy IDE I/O ports on PIIX chipset. However Linux ata_piix
driver does sanity check to see whether legacy ports decode is turned on.
To make Linux ata_piix driver happy, turn on the decode via IDE_TIMING register.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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