<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/arch/x86, branch v2016.03</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86?h=v2016.03</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/arch/x86?h=v2016.03'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2016-02-21T05:42:52Z</updated>
<entry>
<title>x86: Add Intel Cougar Canyon 2 board</title>
<updated>2016-02-21T05:42:52Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-17T08:16:25Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a2e3b05e16c96ccc5929d60457938cd96912d758'/>
<id>urn:sha1:a2e3b05e16c96ccc5929d60457938cd96912d758</id>
<content type='text'>
This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: ivybridge: bd82x6x: Support FSP enabled configuration</title>
<updated>2016-02-21T05:42:52Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-17T08:16:24Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=87077e97d1a72286871d03a6f06903245b9caacd'/>
<id>urn:sha1:87077e97d1a72286871d03a6f06903245b9caacd</id>
<content type='text'>
Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif,
and enable the build for both FSP and non-FSP configurations.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: fsp: Make sure HOB list is not overwritten by U-Boot</title>
<updated>2016-02-21T05:42:52Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-17T08:16:23Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=dc5be508b065ff305cef451ac1aed7465603db02'/>
<id>urn:sha1:dc5be508b065ff305cef451ac1aed7465603db02</id>
<content type='text'>
Intel IvyBridge FSP seems to be buggy that it does not report memory
used by FSP itself as reserved in the resource descriptor HOB. The
FSP specification does not describe how resource descriptor HOBs are
generated by the FSP to describe what memory regions. It looks newer
FSPs like Queensbay and BayTrail do not have such issue. This causes
U-Boot relocation overwrites the important boot service data which is
used by FSP, and the subsequent call to fsp_notify() will fail.

To resolve this, we find out the lowest memory base address allocated
by FSP for the boot service data when walking through the HOB list in
fsp_get_usable_lowmem_top(). Check whether the memory top address is
below the FSP HOB list, and if not, use the lowest memory base address
allocated by FSP as the memory top address.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: ivybridge: Add FSP support</title>
<updated>2016-02-21T05:42:52Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-17T08:16:21Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=437413962744cc9c80551ca253a20472856551f2'/>
<id>urn:sha1:437413962744cc9c80551ca253a20472856551f2</id>
<content type='text'>
IvyBridge FSP package is built with a base address at 0xfff80000,
and does not use UPD data region. This adds basic FSP support.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: fix memalign() parameter order</title>
<updated>2016-02-21T05:42:51Z</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2016-02-12T21:27:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4fd64d02b2bb7fe583c1246c79b9658223d96442'/>
<id>urn:sha1:4fd64d02b2bb7fe583c1246c79b9658223d96442</id>
<content type='text'>
Purely by code inspection, it looks like the parameter order to memalign()
is swapped; its parameters are (align, size). 4096 is a likely desired
alignment, and a variable named size sounds like a size:-)

Fixes: 45b5a37836d5 ("x86: Add multi-processor init")
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging</title>
<updated>2016-02-08T14:48:04Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2016-02-08T14:48:04Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=57dc53a72460e8e301fa1cc7951b41db8e731485'/>
<id>urn:sha1:57dc53a72460e8e301fa1cc7951b41db8e731485</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Use correct spelling of "U-Boot"</title>
<updated>2016-02-06T11:00:59Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-06T03:30:11Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a187559e3d586891c917279044c5386d1b2adc6e'/>
<id>urn:sha1:a187559e3d586891c917279044c5386d1b2adc6e</id>
<content type='text'>
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Heiko Schocher &lt;hs@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
</entry>
<entry>
<title>x86: Drop pci_type1.c and DEFINE_PCI_DEVICE_TABLE</title>
<updated>2016-02-05T04:47:24Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-02T13:58:09Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5c884420a5752163ce738701701ae1874d8f466d'/>
<id>urn:sha1:5c884420a5752163ce738701701ae1874d8f466d</id>
<content type='text'>
Now that we have converted all x86 codes to DM PCI, drop pci_type1.c
which is only built for legacy PCI. Also per checkpatch.pl warning,
DEFINE_PCI_DEVICE_TABLE is now deprecated so drop that too.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Disable DM_PCI_COMPAT</title>
<updated>2016-02-05T04:47:24Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-02T13:58:08Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d8277a87d0993492b2c09dcd9ccf1ce652d03b9c'/>
<id>urn:sha1:d8277a87d0993492b2c09dcd9ccf1ce652d03b9c</id>
<content type='text'>
Now that all x86 codes have been converted to use proper DM PCI APIs,
it's time to disable the legacy compatible layer.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: quark: Use Quark's own PCI config APIs</title>
<updated>2016-02-05T04:47:23Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2016-02-02T13:58:02Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5a257df702e5702f46fca548d0899c65e90df947'/>
<id>urn:sha1:5a257df702e5702f46fca548d0899c65e90df947</id>
<content type='text'>
There are still two places in Quark's MRC codes that use the generic
legacy PCI APIs, but as we are phasing out these legacy APIs, switch
to use Quark's own PCI config routines.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
</feed>
