u-boot.git/arch/x86, branch v2016.05

x86: Correct typo of Miao Yan's email address

2016-04-22T03:26:32Z

Miao Yan's email address is wrong in fw_cfg.c. Fix it. Signed-off-by: Bin Meng

x86: qemu: Drop our own ACPI implementation

2016-04-22T03:26:32Z

Our own ACPI implementation (when CONFIG_QEMU_ACPI_TABLE is not set) does not build anymore after x86 has been fully converted to DM PCI. Instead of trying to fix the build errors, given we now have the ACPI support via QEMU's fw_cfg interface, which is a more reliable way to generate correct ACPI tables than by ourselves, hence drop our own ACPI implementation. Signed-off-by: Bin Meng Reviewed-by: Simon Glass

arm: x86: Drop command-line code when CONFIG_CMDLINE is disabled

2016-03-22T16:16:09Z

Update the link script to drop this code when not needed. This is only done for two architectures at present. Signed-off-by: Simon Glass Reviewed-by: Tom Rini

x86: Add congatec conga-QA3/E3845-4G (Bay Trail) support

2016-03-17T02:27:27Z

This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM, installed on the congatec Qseven 2.0 evaluation carrier board (conga-QEVAL). Its port is very similar to the MinnowboardMAX port and also uses the Intel FSP as described in doc/README.x86. Currently supported are the following interfaces / devices: - UART (via Winbond legacy SuperIO chip on carrier board) - Ethernet (PCIe Intel I210 / E1000) - SPI including SPI NOR as boot-device - USB 2.0 - SATA via U-Boot SCSI IF - eMMC - Video (HDMI output @ 800x600) - PCIe Not supported yet is: - I2C - USB 3.0 Signed-off-by: Stefan Roese Cc: Simon Glass Cc: Bin Meng Reviewed-by: Bin Meng

x86: Add support for the samus chromebook

2016-03-17T02:27:27Z

This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass Reviewed-by: Bin Meng

x86: Support a chained-boot development flow

2016-03-17T02:27:27Z

Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI without any 16-bit init. This can help during development by allowing U-Boot to avoid doing all the init required by the platform. U-Boot expects its GDT to be set up correctly by its 16-bit code. If coreboot doesn't do this (because it hasn't run the payload setup code yet) then this won't happen. In this case we cannot rely on the GDT settings. U-Boot will hang or crash if these are wrong. Provide a development-only option to set up the GDT correctly. This is just a hack so you can jump to U-Boot from any stage of coreboot, not just at the end. Signed-off-by: Simon Glass Reviewed-by: Bin Meng

x86: dts: Drop memory SPD compatible string

2016-03-17T02:27:27Z

This is not needed now that the memory controller driver has the SPD data in its own node. Signed-off-by: Simon Glass Reviewed-by: Bin Meng

x86: ivybridge: Convert to use the common SDRAM code

2016-03-17T02:27:27Z

Adjust the existing implementation to use the new common SDRAM init code. Signed-off-by: Simon Glass Reviewed-by: Bin Meng

x86: Add common SDRAM-init code

2016-03-17T02:27:27Z

The code to call the memory reference code is common to several Intel CPUs. Add common code for performing this init. Intel calls this 'Pre-EFI-Init' (PEI), where EFI stands for Extensible Firmware Interface. Signed-off-by: Simon Glass Reviewed-by: Bin Meng

x86: Move common PCH code into a common place

2016-03-17T02:27:27Z

The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass Reviewed-by: Bin Meng