u-boot.git/arch/x86, branch v2016.09 Unnamed repository; edit this file 'description' to name the repository. x86: efi: Fix EFI 64-bit payload build warnings 2016-08-30T01:26:05+00:00 Bin Meng bmeng.cn@gmail.com 2016-08-25T08:47:18+00:00 3e6cc35f4e8fb5010421e606cfab0e00d0adacc0 There are lots of warnings when building EFI 64-bit payload. include/asm-generic/bitops/__fls.h:17:2: warning: left shift count >= width of type if (!(word & (~0ul << 32))) { ^ In fact, U-Boot itself as EFI payload is running in 32-bit mode. So BITS_PER_LONG needs to still be 32, but EFI status codes are 64-bit when booting from 64-bit EFI. Introduce EFI_BITS_PER_LONG to bridge those status codes with U-Boot's BITS_PER_LONG. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
There are lots of warnings when building EFI 64-bit payload.

include/asm-generic/bitops/__fls.h:17:2:
  warning: left shift count >= width of type
  	if (!(word & (~0ul << 32))) {
			^

In fact, U-Boot itself as EFI payload is running in 32-bit mode.
So BITS_PER_LONG needs to still be 32, but EFI status codes are
64-bit when booting from 64-bit EFI. Introduce EFI_BITS_PER_LONG
to bridge those status codes with U-Boot's BITS_PER_LONG.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
x86: Add debugging when cpu_common_init() fails 2016-08-30T01:26:05+00:00 Simon Glass sjg@chromium.org 2016-07-26T00:58:59+00:00 4cc00f0611c4b491f6dd1f6a5582d24a41f12769 Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Add a debug() at this point to help figure out what is wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: ivybridge: Allow microcode to be collated 2016-08-30T01:26:05+00:00 Simon Glass sjg@chromium.org 2016-07-26T00:58:58+00:00 e6294e0579897a682a823aefc99fe416c78aaf6e Generally the microcode is combined into a single block only (and removed from the device tree) when there are multiple blocks. But this is not a requirement. Adjust the ivybridge code to avoid assuming this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Generally the microcode is combined into a single block only (and removed
from the device tree) when there are multiple blocks. But this is not a
requirement.

Adjust the ivybridge code to avoid assuming this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: Add debugging when a microcode update fails 2016-08-30T01:26:05+00:00 Simon Glass sjg@chromium.org 2016-07-26T00:58:57+00:00 fda4fa8195bab36879272e92973a7ef39e759795 Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher<hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Add a debug() at this point to help figure out what is wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher<hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: Add theadorable-x86-dfi-bt700 board support 2016-08-16T03:44:09+00:00 Stefan Roese sr@denx.de 2016-08-15T11:50:59+00:00 27daffe7cec26ec1462245e4e15c36d19d886221 This patch adds support for the BayTrail based theadorable-x86-dfi-bt700 board which uses the DFI BT700 BayTrail Qseven SoM on a custom baseboard. The main difference to the DFI baseboard is, that it isn't equipped with a Super IO chip and uses the internal HS SIO UART (memory mapped PCI based) as the console UART. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
This patch adds support for the BayTrail based theadorable-x86-dfi-bt700
board which uses the DFI BT700 BayTrail Qseven SoM on a custom baseboard.
The main difference to the DFI baseboard is, that it isn't equipped
with a Super IO chip and uses the internal HS SIO UART (memory mapped
PCI based) as the console UART.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: Add DFI BT700 BayTrail board support 2016-08-16T03:44:09+00:00 Stefan Roese sr@denx.de 2016-08-15T11:50:49+00:00 b1ad6c696631f07b5fe109378516abcb79ded1f9 This patch adds support for the DFI BayTrail BT700 QSeven SoM installed on the DFI Q7X-151 baseboard. The baseboard is equipped with the Nuvoton NCT6102D Super IO chip providing the UART as console. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
This patch adds support for the DFI BayTrail BT700 QSeven SoM installed
on the DFI Q7X-151 baseboard. The baseboard is equipped with the Nuvoton
NCT6102D Super IO chip providing the UART as console.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: conga-qeval20-qa3: Add SMBus support and SMSC2513 config code 2016-08-16T03:44:09+00:00 Stefan Roese sr@denx.de 2016-06-28T13:45:13+00:00 303dfc2e5efeaebfb7f01f2e59e5870e645376ca This patch includes the following changes: - Remove Designware I2C support from dts as its not used - Configure SMBus PADs in dts - Enable I2C commands and I2C support - Configure SMSC2513 USB hub via SMBus upon startup - Move environment location to match Minnowmax example - Enhancement of the default environment Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
This patch includes the following changes:

- Remove Designware I2C support from dts as its not used
- Configure SMBus PADs in dts
- Enable I2C commands and I2C support
- Configure SMSC2513 USB hub via SMBus upon startup
- Move environment location to match Minnowmax example
- Enhancement of the default environment

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
i2c: intel_i2c: SMBus driver PCI addition (e.g. BayTrail) 2016-08-16T03:44:09+00:00 Stefan Roese sr@denx.de 2016-08-09T05:41:15+00:00 ca6c5e03f132e9042c27472650184be9e8263508 This patch adds support for the SMBus block read/write functionality. Other protocols like the SMBus quick command need to get added if this is needed. This patch also removed the SMBus related defines from the Ivybridge pch.h header. As they are integrated in this driver and should be used from here. This change is added in this patch to avoid compile breakage to keep the source git bisectable. Tested on a congatec BayTrail board to configure the SMSC2513 USB hub. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
This patch adds support for the SMBus block read/write functionality.
Other protocols like the SMBus quick command need to get added
if this is needed.

This patch also removed the SMBus related defines from the Ivybridge
pch.h header. As they are integrated in this driver and should be
used from here. This change is added in this patch to avoid compile
breakage to keep the source git bisectable.

Tested on a congatec BayTrail board to configure the SMSC2513 USB
hub.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
x86: som-db5800-som-6867: fix SERIRQ on reset 2016-08-16T03:44:09+00:00 George McCollister george.mccollister@gmail.com 2016-07-28T14:49:37+00:00 144fdbdeb1f5cbf3ee99300f7d903da373b0a90d Explicitly enable ILB_SERIRQ function 1 in cfio_regs_pad_ilb_serirq_PCONF0. Pad configuration for SERIRQ is not set to enable the SERIRQ function after a reset though strangely, it is on initial boot. Rebooting from Linux, reset command in u-boot and even pushing the reset button on the development board all lead to the SERIRQ function being disabled (address 0xfed0c560 with value of 0x2003cc80). Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Explicitly enable ILB_SERIRQ function 1 in
cfio_regs_pad_ilb_serirq_PCONF0.

Pad configuration for SERIRQ is not set to enable the SERIRQ function
after a reset though strangely, it is on initial boot.

Rebooting from Linux, reset command in u-boot and even pushing the reset
button on the development board all lead to the SERIRQ function being
disabled (address 0xfed0c560 with value of 0x2003cc80).

Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: baytrail: Add SIO HS-UART clock setup 2016-08-16T03:44:09+00:00 Stefan Roese sr@denx.de 2016-07-19T05:41:25+00:00 d7b935bf62bafdf5fbe4734c7536754948958890 To support the BayTrail internal SIO HS UART, the internal UART clock needs to get configured. This patch adds support for this clock configuration which will be done, if the PCI device(s) are found. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
To support the BayTrail internal SIO HS UART, the internal UART clock
needs to get configured. This patch adds support for this clock
configuration which will be done, if the PCI device(s) are found.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>