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<title>u-boot.git/arch/x86, branch v2017.03</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86?h=v2017.03</id>
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<updated>2017-02-21T07:10:56Z</updated>
<entry>
<title>x86: Intel MID platforms has no microcode update</title>
<updated>2017-02-21T07:10:56Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2017-02-17T13:49:00Z</published>
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<id>urn:sha1:308c75e08deac2933fbc63a1e9521343e710279c</id>
<content type='text'>
There is no microcode update available for SoCs used on Intel MID
platforms.

Use conditional to bypass it.

Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>x86: zImage: add Intel MID platforms support</title>
<updated>2017-02-21T07:10:50Z</updated>
<author>
<name>Vincent Tinelli</name>
<email>vincent.tinelli@intel.com</email>
</author>
<published>2017-02-17T13:48:59Z</published>
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<id>urn:sha1:20bfac0599bd7eaad901287fe4a343f9fd6cf6ef</id>
<content type='text'>
Intel MID platform boards have special treatment, such as boot parameter
setting.

Assign hardware_subarch accordingly if CONFIG_INTEL_MID is set.

Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Vincent Tinelli &lt;vincent.tinelli@intel.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>x86: Introduce INTEL_MID quirk option</title>
<updated>2017-02-21T07:10:46Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2017-02-17T13:48:58Z</published>
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<id>urn:sha1:7a96fd8ef002e85ccd8ae5907de9d45fc9002c36</id>
<content type='text'>
Intel Mobile Internet Device (MID) platforms have special treatment in
some cases, such as CPU enumeration or boot parameters configuration.

Besides that several drivers are specifically developed for the IP
blocks found on Intel MID platforms. Those drivers will be dependent to
this option.

Here we introduce specific quirk option for such cases.

It is supposed to be selected by Intel MID platform boards, for example,
Intel Edison.

Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>x86: Force 32-bit jumps in interrupt handlers</title>
<updated>2017-02-21T06:53:29Z</updated>
<author>
<name>J. Tang</name>
<email>tang@jtang.org</email>
</author>
<published>2017-02-10T02:54:13Z</published>
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<id>urn:sha1:3c03f4928e96dce4c6cd14fb630dacad13a141ae</id>
<content type='text'>
Depending upon the compiler used, IRQ entries could vary in sizes. With
GCC 5.x, the code generator will use short jumps for some IRQ entries
but near jumps for others. For example, GCC 5.4.0 generates the
following:

$ objdump -d interrupt.o
&lt;snip&gt;
00000207 &lt;irq_18&gt;:
207:   6a 12                   push   $0x12
209:   eb 85                   jmp    190 &lt;irq_common_entry&gt;

0000020b &lt;irq_19&gt;:
20b:   6a 13                   push   $0x13
20d:   eb 81                   jmp    190 &lt;irq_common_entry&gt;

0000020f &lt;irq_20&gt;:
20f:   6a 14                   push   $0x14
211:   e9 7a ff ff ff          jmp    190 &lt;irq_common_entry&gt;

00000216 &lt;irq_21&gt;:
216:   6a 15                   push   $0x15
218:   e9 73 ff ff ff          jmp    190 &lt;irq_common_entry&gt;

This causes a problem in cpu_init_interrupts(), because the IDT setup
assumed same sizes for all IRQ entries. GCC 4.x always generated 32-bit
jumps, so this previously was not a problem.

The fix is to force 32-bit near jumps for all entries within the
inline assembly. This works for GCC 5.x, and 4.x was already using
that form of jumping.

Signed-off-by: Jason Tang &lt;tang@jtang.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>dm: core: Replace of_offset with accessor</title>
<updated>2017-02-08T13:12:14Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-01-17T23:52:55Z</published>
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<id>urn:sha1:e160f7d430f163bc42757aff3bf2bcac0a459f02</id>
<content type='text'>
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: make LOAD_FROM_32_BIT visible for platforms</title>
<updated>2017-02-07T05:36:50Z</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2017-02-05T13:52:00Z</published>
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<id>urn:sha1:446d4e048ee3b00f7907e15cd02aa404cc714c77</id>
<content type='text'>
This option is useful not only for development, but for the platforms
where U-Boot is run from custom ROM bootloader. For example, Intel
Edison is that board.

Make this option visible that platforms can select it if needed.

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: qemu: Mark ucode as optional for SPL in u-boot.dtsi</title>
<updated>2017-02-07T05:27:13Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-01-18T11:32:58Z</published>
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<id>urn:sha1:399de922ff74a215964cd039c5025538f75e6b73</id>
<content type='text'>
QEMU does not need ucode and this is indicated in u-boot.dtsi
for U-Boot proper. Now add the same for SPL.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: qemu: Set up device tree for SPL</title>
<updated>2017-02-07T05:27:11Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-01-18T11:32:57Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2cffd90f14de4fafe953145f3a72fd0fdbf631b2'/>
<id>urn:sha1:2cffd90f14de4fafe953145f3a72fd0fdbf631b2</id>
<content type='text'>
Add the correct pre-relocation tag so that the required device tree
nodes are present in the SPL device tree.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: qemu: Fix compiler warnings for 64-bit</title>
<updated>2017-02-07T05:27:08Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-01-18T11:32:56Z</published>
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<id>urn:sha1:63767071d977d428264769fe7923da6a59cb166b</id>
<content type='text'>
This fixes compiler warnings for QEMU in 64-bit.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: qemu: Hide arch_cpu_init() and print_cpuinfo() for U-Boot proper</title>
<updated>2017-02-07T05:23:42Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-01-18T11:32:55Z</published>
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<id>urn:sha1:e760feb19f227d830d0a0751a42a2cf5dbcefa28</id>
<content type='text'>
arch_cpu_init() and print_cpuinfo() should be only available in SPL
build.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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