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<title>u-boot.git/arch/x86, branch v2017.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch/x86?h=v2017.07</id>
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<updated>2017-06-27T08:31:30Z</updated>
<entry>
<title>Revert "x86: Convert MMC to driver model"</title>
<updated>2017-06-27T08:31:30Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-06-26T23:36:15Z</published>
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<id>urn:sha1:da2364cc14a0b34411c4a228ae687a23504afe04</id>
<content type='text'>
This reverts commit ddb3ac3c716f56cead695444e65a7ba7b0946555.

With MMC converted to driver model, SCSI driver is broken due to
zero address access at (ops-&gt;read) in block_dread() function.

The fix (SCSI driver converted to DM) is ready in u-boot-dm branch,
but it is too late for this relese to get that in.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Don't include asm/u-boot.h in common</title>
<updated>2017-06-05T15:02:35Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-05-17T14:22:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3ff240c92f516841d8aff3b7d9268763711f2afd'/>
<id>urn:sha1:3ff240c92f516841d8aff3b7d9268763711f2afd</id>
<content type='text'>
With a small fixup to u-boot-x86.h, this is not actually needed anywhere,
so drop it.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: Make u-boot-x86.h a private header</title>
<updated>2017-06-05T15:02:32Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-05-17T14:22:49Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6862b50f6eebf4379e6d3b74a64378988e8e2961'/>
<id>urn:sha1:6862b50f6eebf4379e6d3b74a64378988e8e2961</id>
<content type='text'>
Rather than including this arch-specific header file in common.h, include
it from within x86's u-boot.h header.

Also drop the comment about something to be fixed. It is not clear what
needs fixing.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: fsp: Remove the call to set up internal uart in fsp_init()</title>
<updated>2017-06-05T00:55:22Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-06-01T10:41:14Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d7f7ba36b2edecb16393f8373cca833adb8ea6c3'/>
<id>urn:sha1:d7f7ba36b2edecb16393f8373cca833adb8ea6c3</id>
<content type='text'>
First of all, it's inappropriate to call setup_internal_uart() in a
generic API fsp_init(), as CONFIG_INTERNAL_UART is an option that
is only available on BayTrail platform. Secondly even for BayTrail,
there is no need to call setup_internal_uart() at all, as Intel FSP
will do this for us.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: baytrail: Fix boot hang with a debug build</title>
<updated>2017-06-05T00:55:22Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-06-01T10:41:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=37d1023264e7b73b72e0c42fd55de91c7018135d'/>
<id>urn:sha1:37d1023264e7b73b72e0c42fd55de91c7018135d</id>
<content type='text'>
It was observed that when -DDEBUG is used to generate a debug build,
U-Boot does not boot on MinnowMax board. A workaround is to disable
CONFIG_DEBUG_UART. The real issue is that in order to have the debug
uart to work, BayTrail SoC needs to be configured so that its internal
uart is available to be used as the debug uart.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: baytrail: Change lpe/lpss-sio/scc FSP properties to integer</title>
<updated>2017-06-05T00:55:22Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-05-31T08:04:15Z</published>
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<id>urn:sha1:f8f291b0962c795fcb025338d5c2284e2357a669</id>
<content type='text'>
At present lpe/lpss-sio/scc FSP properties are all boolean, but in
fact for "enable-lpe" it has 3 possible options. This adds macros
for these options and change the property from a boolean type to
an integer type, and change their names to explicitly indicate what
the property is really for.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: baytrail: Use macros instead of magic numbers for FSP settings</title>
<updated>2017-06-05T00:55:22Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-05-31T08:04:14Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5e74e5a6826f8cf194ef5a569d6cafd2ed924f5c'/>
<id>urn:sha1:5e74e5a6826f8cf194ef5a569d6cafd2ed924f5c</id>
<content type='text'>
Introduce various meaningful macros for FSP settings and switch over
to use them instead of magic numbers.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: baytrail: Remove "serial-debug-port-*" settings</title>
<updated>2017-06-05T00:55:22Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-05-31T08:04:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6702488cfa90831454d83a63eb0b4a0bb82a3a1f'/>
<id>urn:sha1:6702488cfa90831454d83a63eb0b4a0bb82a3a1f</id>
<content type='text'>
"serial-debug-port-address" and "serial-debug-port-type" settings
are actually reserved in the FSP UPD data structure. Remove them.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: baytrail: Change "fsp, mrc-init-tseg-size" default value to 1</title>
<updated>2017-06-05T00:55:22Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-05-31T08:04:12Z</published>
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<id>urn:sha1:455a5a8086b17bd6fb60c86ec34299cae6ce2950</id>
<content type='text'>
The default value of "fsp,mrc-init-tseg-size" should be 1 (1MB) per
FSP default settings. 0 is not valid.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: minnowmax: Remove incorrect pad-offset of several pins</title>
<updated>2017-05-17T09:13:06Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2017-05-08T02:52:30Z</published>
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<id>urn:sha1:c2f17939f4b429c90a453e26927a7c578e5456b5</id>
<content type='text'>
Remove 'pad-offset' of soc_gpio_s5_0, soc_gpio_s5_1, soc_gpio_s5_2,
pin_usb_host_en0 and pin_usb_host_en1. These offsets are actually
wrong. Correct value should be added by 0x2000, but since they
are supposed to be 'mode-gpio', 'pad-offset' is not needed at all.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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