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Merge patch series "TI: AM64-EVM/SK: Enable MAIN UART1 for SYSFW tracing"

2026-07-03T16:10:34Z

Vishal Mahaveer says: Collecting SYSFW traces from DMSC firmware is broken on the current codebase. These changes enables MAIN_UART1 for collecting SYSFW traces when the trace option is enabled in the boardcfg. Link: https://lore.kernel.org/r/20260605193829.395161-1-vishalm@ti.com

arm: dts: k3-am642-evm/sk: enable MAIN UART1 for SYSFW logs

2026-07-03T16:09:56Z

Enable MAIN UART1 in the R5 SPL device tree to collect system SYSFW debug traces during early boot. Signed-off-by: Vishal Mahaveer Reviewed-by: Bryan Brattlof

arm: mach-k3: am642: Update MAIN UART1 serial alias from 3 to 1

2026-07-03T16:09:56Z

The upstream device tree changed the serial alias for MAIN UART1 from serial3 to serial1. Update the board initialization code to match this change by modifying the UCLASS_SERIAL sequence number lookup. This ensures proper pin control configuration for the UART used by system firmware (SYSFW). Signed-off-by: Vishal Mahaveer Fixes: d2edabfa8de5 ("arm: mach-k3: am642: Load SYSFW binary and config from boot media") Reviewed-by: Bryan Brattlof

rockchip: sdram: Fix initialization of DRAM banks

2026-06-30T19:38:12Z

The commit 55a342176984 ("common: Add an option to relocate on ram top") changed so that dram_init_banksize() is called before gd->ram_top has been initialized. This change broke Rockchip DRAM banks configuration due to gd->ram_top now being 0 when dram_init_banksize() is called. This makes first DRAM bank size calculation overflow and end up with DRAM bank = 0x0000000000000000 -> start = 0x0000000000200000 -> size = 0xffffffffffe00000 instead of the expected (for 2 GiB) DRAM bank = 0x0000000000000000 -> start = 0x0000000000200000 -> size = 0x000000007fe00000 or (for 4 GiB) DRAM bank = 0x0000000000000000 -> start = 0x0000000000200000 -> size = 0x00000000f7e00000 on e.g. RK3399 boards. Change to not depend on gd->ram_top having to be pre-calculated before dram_init_banksize() is called, also move the related method board_get_usable_ram_top() closer to more easily get an overview of their interdependence, to restore working DRAM bank initialization. Fixes: 55a342176984 ("common: Add an option to relocate on ram top") Signed-off-by: Jonas Karlman Reported-by: Ilias Apalodimas Acked-by: Ilias Apalodimas Tested-by: Ilias Apalodimas # on Radxa ROCK

Merge patch series "arm: aspeed: add initial AST2700 SoC support"

2026-06-29T21:29:56Z

Ryan Chen says: AST2700 is the 8th generation of Integrated Remote Management Processor introduced by ASPEED Technology Inc. It is a Board Management Controller (BMC) SoC family with a dual-die architecture: SoC0 ("CPU" die with four ARM Cortex-A35 application cores) and SoC1 ("IO" die with peripherals) each SoC have its own SCU PLLs, clock dividers and reset domains. Link: https://lore.kernel.org/r/20260612-ast2700_clk-v4-0-9bea29cfdc39@aspeedtech.com

treewide: Staticize and constify acpi ops

2026-06-29T21:29:44Z

Set the acpi_ops structure as static const where applicable. The The structure is not accessible from outside of drivers and is not going to be modified at runtime. The structure may be unused in a couple of drivers depending on their configuration, mark those sites with __maybe_unused . Signed-off-by: Marek Vasut Reviewed-by: Simon Glass

ram: aspeed: add SDRAM controller driver for AST2700

2026-06-29T19:43:21Z

Add a SDRAM controller driver for the AST2700, derived from the existing AST2700 controller code used by the Ibex SPL but adapted to run from ARM U-Boot proper on the Cortex-A35 cores. The DDR4/DDR5 controller and its DesignWare PHY are programmed by the Ibex SPL before ARM U-Boot proper takes over. This driver reads back the configuration left by the SPL, probes the controller, and exposes ram_info (base and size, with the VGA carve-out subtracted) via UCLASS_RAM so that dram_init() can populate gd->ram_size. The PHY firmware-load entry points (dwc_ddrphy_phyinit_userCustom_*) are kept compiled but call a __weak fmc_hdr_get_prebuilt() stub when ARM U-Boot proper is the caller; the real implementation is provided by the Ibex SPL via the same fmc_hdr.h descriptor format (here added for the ARM build). Adds the supporting register-layout headers under arch/arm/include/asm/arch-aspeed/: - sdram.h: SDRAM controller and DWC PHY register definitions - scu.h: SCU bits referenced by the SDRAM driver - fmc_hdr.h: prebuilt-blob descriptor (binary-compatible with arch/riscv/include/asm/arch-ast2700/fmc_hdr.h used by the Ibex SPL) Signed-off-by: Ryan Chen

arm: dts: aspeed: Add initial AST27xx SoC device tree

2026-06-29T19:43:20Z

Add initial device tree support for the ASPEED AST27xx family, the 8th-generation Baseboard Management Controller (BMC) SoCs. AST27xx SOC Family - https://www.aspeedtech.com/server_ast2700/ - https://www.aspeedtech.com/server_ast2720/ - https://www.aspeedtech.com/server_ast2750/ The AST27xx features a dual-SoC architecture consisting of two ties, referred to as SoC0 and SoC1 - interconnected through an internal property bus. Both SoCs share the same address decoding scheme, while each maintains independent clock and reset domains. - SoC0 (CPU die): contains a dual-core Cortex-A35 cluster and two Cortex-M4 cores, along with high-speed peripherals. - SoC1 (I/O die): includes the BootMCU (responsible for system boot) and its own clock/reset domains low-speed peripherals. The device tree describes the SoC0 and SoC1 domains and their peripheral layouts. Signed-off-by: Ryan Chen

arm: aspeed: add ASPEED AST2700 SoC family support

2026-06-29T19:43:20Z

Add initial support for the ASPEED AST2700, an arm64 (Cortex-A35) Baseboard Management Controller (BMC) SoC. AST2700 is Aspeed's 8th generation BMC and uses a dual-die architecture: SoC0 (the "CPU" die) hosts the four Cortex-A35 cores and its own SCU at 0x12c02000, while SoC1 (the "IO" die) hosts the peripherals and its own SCU at 0x14c02000. This commit adds: - ASPEED_AST2700 Kconfig option and the ast2700 mach subdir (mach Makefile, ast2700/Kconfig, board/aspeed/evb_ast2700/*) - arm64 MMU map covering the SoC device window and the DRAM region at 0x4_0000_0000 (up to 8 GiB) - lowlevel_init.S for early CPU bring-up - cpu-info: print SoC ID (AST2700/2720/2750 A0/A1/A2 variants) and reset cause (cold reset, EXT reset, WDT reset) - board_common: dram_init via UCLASS_RAM, AHBC timeout init - platform: env_get_location() that selects SPI/eMMC based on the IO-die HW strap; arch_misc_init() that exposes ${boot_device} and ${verify} to the boot script - SCU0/SCU1 register layout header (scu_ast2700.h) - configs/evb-ast2700_defconfig and include/configs/evb_ast2700.h for the AST2700 EVB board The defconfig depends on ast2700-evb.dts, which is introduced in a subsequent patch; this commit must be applied with the remaining series for evb-ast2700_defconfig to build. Signed-off-by: Ryan Chen

imx9: Add v2x_status and ele_info commands

2026-06-27T02:02:46Z

Add v2x_status and ele_info commands to print useful information for development and debug purpose. Signed-off-by: Ye Li