This code is no-longer used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>

Seen this one in the wild. Is labelled "Raspberry Pi Model A+ V1.1,
(C) Raspberry Pi 2014". A standard A+ board, much like the one with
version 0x12, didn't notice any differencies.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>

On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>"
and based on the previous work done by "Hao Zhang <hzhang@ti.com>"

Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: Vitaly Andrianov <vitalya@ti.com>
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

There are various toolchain issues that cause us to produce invalid
binaries with certain gcc 4.8.x and 4.9.x versions when we don't pass
this flag in.

Tested-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Signed-off-by: Tom Rini <trini@konsulko.com>

We need "u-boot,dm-pre-reloc" in the socfpga_cyclone5_socdk.dts file in
order for the SPL to use SD/MMC.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Update the L2 AUX CTRL settings for the SoCFPGA.

Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.

Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has the
side effect of transforming Normal Shared Non-cacheable reads into Cacheable
no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Add 'volatile' qualifier to the asm statement in get_cr()
so that the statement is not optimized out by the compiler.

(http://comments.gmane.org/gmane.linux.linaro.toolchain/5163)

Without the 'volatile', get_cr() returns a wrong value which
prevents enabling the MMU  and later causes a PCIE VA access
failure.

Signed-off-by: Alison Wang <alison.wang@freescale.com>