u-boot.git/arch, branch v2016.09-rc1

Merge git://git.denx.de/u-boot-nand-flash

2016-07-25T18:49:54+00:00

ARM: am33xx: Always inhibit init/refresh during DDR phy init

2016-07-25T16:00:06+00:00

A couple of commits have modified the am33xx/am437x ddr2/ddr3
initialization path to fix certain issues, but have had the side effect
of causing L3 noc errors during initialization. The two commits are:

69b918 "am33xx,ddr3: fix ddr3 sdram configuration"
fc46ba "arm: am437x: Enable hardware leveling for EMIF"

The EMIF_REG_INITREF_DIS_MASK bit still needs to be set for all
platforms. This delays initialization and refresh until a later stage.
The 500us timer can be programmed for platforms that require it
and for platforms that don't require it. It is currently hardcoded
for 400MHz systems. For systems with a higher memory frequency
this needs to be a larger value, and for systems with a lower
memory frequency this can be a lower value. This can be
considered a separate issue and corrected in a later commit.

Signed-off-by: Russ Dill 
Reviewed-by: Tom Rini

ARM: am33xx: Fix DDR init delay placement

2016-07-25T16:00:06+00:00

The delay needs to be before the write to ref_ctrl register
which initiates refreshes. An improper initialization sequence
generates an L3 noc error.

Signed-off-by: Russ Dill 
Reviewed-by: Tom Rini

keystone: k2h/e/l: Fix DMA coherency for QM PDSP

2016-07-25T16:00:05+00:00

commit 1f807a9f32aa ("ARM: keystone2: Refactor MSMC macros to avoid
left under a macro KS2_MSMC_SEGMENT_QM_PDSP which is no longer valid.
This, in effect disabled DMA coherency for QM PDSP.

Given that msmc_k2hkle_common_setup is valid for all K2H/K/L/E SoCs,
the #ifdef should been removed in the first place. Do the same.

Fixes: 1f807a9f32aa ("ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery")
Signed-off-by: Murali Karicheri 
Acked-by: Nishanth Menon 
Reviewed-by: Tom Rini

sunxi: Enable NAND controller on the CHIP

2016-07-25T01:36:29+00:00

Enable the NAND controller in the sun5i-r8-chip.dts.

Signed-off-by: Boris Brezillon 
Acked-by: Hans de Goede

sun5i: Add NAND controller to the sun5i DTSI

2016-07-25T01:36:28+00:00

Add the NAND controller definition to sun5i.dtsi.

Signed-off-by: Maxime Ripard 
Signed-off-by: Boris Brezillon

sunxi: Add missing macros to configure the NAND controller clk

2016-07-25T01:36:28+00:00

We need some macros to manipulate the NAND controller clock.

Signed-off-by: Boris Brezillon 
Acked-by: Hans de Goede

ARM: uniphier: add clock/reset settings for xHCI of ProXstream2

2016-07-23T15:44:55+00:00

Deassert resets and enable clock signals of xHCI blocks if the
corresponding CONFIG is enabled.

Signed-off-by: Masahiro Yamada

ARM: uniphier: add PH1-LD21 board data

2016-07-23T15:24:58+00:00

This has the same silicon die as PH1-LD20, but includes DRAM chips
in its package.

Signed-off-by: Masahiro Yamada

ARM: uniphier: introduce flags to uniphier_board_data structure

2016-07-23T15:24:55+00:00

I need to add more board attributes, so the "flags" member will be
handier than separate boolean ones.

Signed-off-by: Masahiro Yamada