u-boot.git/arch, branch v2017.01-rc1

Merge git://git.denx.de/u-boot-fsl-qoriq

2016-12-05T22:00:23Z

armv8: QSPI: Add AHB bus 16MB+ size support

2016-12-05T16:32:43Z

The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: Yuan Yao Reviewed-by: York Sun

ls1021a: QSPI: update the node for QSPI support

2016-12-05T16:31:45Z

Add the name for register space and memory space. <0x1550000 0x10000 > is the QSPI register space. <0x40000000 0x4000000> is the QSPI memory space. Signed-off-by: Yuan Yao Reviewed-by: York Sun

armv8: ls2080a: Add serdes1 protocol 0x3b support

2016-12-05T16:31:45Z

Signed-off-by: Priyanka Jain Reviewed-by: York Sun

fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum

2016-12-05T16:31:45Z

- add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun

Merge git://www.denx.de/git/u-boot-i2c

2016-12-05T16:02:01Z

arm64: mvebu: Restrict memory size to a usable maximum

2016-12-05T12:34:33Z

Not all memory is mapped in the MMU. So we need to restrict the memory size so that U-Boot does not try to access it. Also, the internal registers are located at 0xf000.0000 - 0xffff.ffff. Currently only 2GiB are mapped for system memory. This is what we pass to the U-Boot subsystem here. Signed-off-by: Stefan Roese Cc: Nadav Haklai Cc: Neta Zur Hershkovits Cc: Kostya Porotchkin Cc: Omri Itach Cc: Igal Liberman Cc: Haim Boot Cc: Hanna Hawa

arm64: mvebu: Add regions for PCI spaces to the memory map

2016-12-05T12:34:33Z

To use the PCIe driver, its controller memory and the PCIe regions need to get mapped in the MMU. Otherwise these areas can't be accessed. Signed-off-by: Stefan Roese Cc: Nadav Haklai Cc: Neta Zur Hershkovits Cc: Kostya Porotchkin Cc: Omri Itach Cc: Igal Liberman Cc: Haim Boot Cc: Hanna Hawa

arm64: mvebu: Init COMPHY from the slave-CP on the A8k

2016-12-05T12:28:23Z

The Armada8k implements 2 CPs (communication processors) and the 2nd CP also is equipped with a COMPHY controller. This patch now loops over all enabled MISC devices (CP110) enabled in the DT to initialize all CPs. Signed-off-by: Stefan Roese Cc: Nadav Haklai Cc: Neta Zur Hershkovits Cc: Kostya Porotchkin Cc: Omri Itach Cc: Igal Liberman Cc: Haim Boot Cc: Hanna Hawa

arm64: mvebu: armada-8040-db.dts: Add I2C and SPI aliases

2016-12-05T12:28:23Z

Add I2C and SPI aliases to enable usage in U-Boot. Otherwise U-Boot will not be able to use the SPI NOR chip for environment storage and use "i2c dev 0" to select this I2C bus. Signed-off-by: Stefan Roese Cc: Nadav Haklai Cc: Neta Zur Hershkovits Cc: Kostya Porotchkin Cc: Omri Itach Cc: Igal Liberman Cc: Haim Boot Cc: Hanna Hawa