u-boot.git/arch, branch v2017.03-rc1

ARM: uniphier: compile board data only for SPL

2017-01-29T11:59:08+00:00

Now U-Boot proper need not get the uniphier_boards array.  Compile
it only for SPL.

Signed-off-by: Masahiro Yamada

ARM: uniphier: refactor cmd_ddrmphy

2017-01-29T11:59:08+00:00

Make it look like cmd_ddrphy.

Signed-off-by: Masahiro Yamada

ARM: uniphier: clean up UMC init for PXs2 SoC

2017-01-29T11:59:08+00:00

Just cosmetic changes:
  - Rename prefix DMPHY_ to MPHY_ for consistency
  - Move UMC parameters below for complete decouple of PHY and UMC
  - Remove redundant whitespaces

Signed-off-by: Masahiro Yamada

ARM: uniphier: refactor cmd_ddrphy

2017-01-29T11:59:08+00:00

It seems more readable to use arrays to get SoC specific parameters
instead of the crappy switch statement.

Signed-off-by: Masahiro Yamada

ARM: uniphier: use gd->bd->bi_dram for memory reserve on LD20 SoC

2017-01-29T11:59:08+00:00

For LD20 SoC, the last 64 byte of each DRAM bank is used for the
dynamic training of DRAM PHY.  The regions must be reserved in DT to
prevent the kernel from using them.  Now gd->bd->bi_dram reflects
the actual memory banks.  Just use it instead of getting access to
the board parameters.

Signed-off-by: Masahiro Yamada

ARM: uniphier: detect RAM size by decoding HW register instead of DT

2017-01-29T11:59:08+00:00

U-Boot needs to set up available memory area(s) in dram_init() and
dram_init_banksize().  It is platform-dependent how to detect the
memory banks.  Currently, UniPhier adopts the memory banks _alleged_
by DT.  This is based on the assumption that users bind a correct DT
in their build process.

Come to think of it, the DRAM controller has already been set up
before U-Boot is entered (because U-Boot runs on DRAM).  So, the
DRAM controller setup register seems a more reliable source of any
information about DRAM stuff.  The DRAM banks are initialized by
preliminary firmware (SPL, ARM Trusted Firmware BL2, or whatever),
so this means the source of the reliability is shifted from Device
Tree to such early-stage firmware.  However, if the DRAM controller
is wrongly configured, the system will crash.  If your system is
running, the DRAM setup register is very likely to provide the
correct DRAM mapping.

Decode the SG_MEMCONF register to get the available DRAM banks.
The dram_init() and dram_init_banksize() need similar decoding.
It would be nice if dram_init_banksize() could reuse the outcome
of dram_init(), but global variables are unavailable at this stage
because the .bss section is available only after the relocation.
As a result, SG_MEMCONF must be checked twice, but a new helper
uniphier_memconf_decode() will help to avoid code duplication.

Signed-off-by: Masahiro Yamada

ARM: uniphier: shrink arrays of DDR-PHY parameters for LD20 SoC

2017-01-29T11:59:08+00:00

The two arrays ddrphy_{op,ip}_dq_shift_val, occupy more than 3.8 KB
memory footprint, which is significant in SPL.

There are PHY parameters for 5 boards, but they are actually not
board specific, but SoC specific.  After all, we just need to have
2 patterns, for LD20 and LD21.  Also, the shift values are small
enough to become "short" type instead of "int".  This change will
save about 3 KB memory footprint.

Signed-off-by: Masahiro Yamada

ARM: SPI: stm32: add stm32f746 qspi driver

2017-01-28T19:04:50+00:00

This patch adds support for the QSPI IP found in stm32f7 devices.

Signed-off-by: Michael Kurz

net: stm32: add designware mac glue code for stm32

2017-01-28T19:04:47+00:00

This patch adds glue code required for enabling the designware
mac on stm32f7 devices.

Signed-off-by: Michael Kurz 
Acked-by: Joe Hershberger

ARM: stm32: use clock setup function defined in clock.c

2017-01-28T19:04:45+00:00

Use the clock setup function defined in clock.c instead of setting the
clock bits directly in the drivers.
Remove register definitions of RCC in rcc.h as these are already
defined in the struct in stm32.h

Signed-off-by: Michael Kurz 
Reviewed-by: Joe Hershberger 
Reviewed-by: Vikas Manocha