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<title>u-boot.git/arch, branch v2017.05-rc1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch?h=v2017.05-rc1</id>
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<updated>2017-04-04T20:01:02Z</updated>
<entry>
<title>Merge git://git.denx.de/u-boot-tegra</title>
<updated>2017-04-04T20:01:02Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-04-04T20:01:02Z</published>
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<id>urn:sha1:3b19c1dbe0464d1cdf3b3006042cc75bc439321f</id>
<content type='text'>
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</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-arc</title>
<updated>2017-04-04T13:20:03Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-04-04T13:20:03Z</published>
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<id>urn:sha1:4951e9420e179977f49549e25d8fd6437b37da72</id>
<content type='text'>
In this patch-set we add support of new AXS103 firmware as well as
troubleshoot unexpected execution by multiple cores simultaneously.
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-dm</title>
<updated>2017-04-04T13:18:57Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-04-04T13:18:57Z</published>
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<id>urn:sha1:7d67bb1daf2daae7bce49147494f8c45001e76b1</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge git://www.denx.de/git/u-boot-marvell</title>
<updated>2017-04-04T13:17:56Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-04-04T13:17:56Z</published>
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<id>urn:sha1:f532703665ae5e5957211bbc4e7296a8313cc403</id>
<content type='text'>
This includes Marvell mvpp2 patches with the ethernet support for the
ARMv8 Armada 7k/8k platforms. The ethernet patches are all acked by Joe
and he is okay with me pushing them via the Marvell tree.
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-fsl-qoriq</title>
<updated>2017-04-04T13:17:08Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-04-04T13:17:08Z</published>
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<id>urn:sha1:797f165f7ae90a75579ae3df7932d8d1518e8544</id>
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</content>
</entry>
<entry>
<title>mmc: tegra: allow disabling external clock loopback</title>
<updated>2017-04-01T22:45:04Z</updated>
<author>
<name>Marcel Ziswiler</name>
<email>marcel.ziswiler@toradex.com</email>
</author>
<published>2017-03-25T00:18:22Z</published>
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<id>urn:sha1:4119b7098c8ef83105946502bc7098dec67bd15d</id>
<content type='text'>
Introduce CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK to disable the external clock
loopback and use the internal one on SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0
register's SDMMC_SPARE1 bits being set to 0xfffd according to the TRM.

Signed-off-by: Marcel Ziswiler &lt;marcel.ziswiler@toradex.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;

Signed-off-by: Marcel Ziswiler &lt;marcel@ziswiler.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>arm: tegra: initial support for apalis tk1</title>
<updated>2017-04-01T22:44:36Z</updated>
<author>
<name>Marcel Ziswiler</name>
<email>marcel.ziswiler@toradex.com</email>
</author>
<published>2017-04-01T22:43:16Z</published>
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<id>urn:sha1:f38f5f4bcf8027041e8c5b9ea3bc1ae905510bc0</id>
<content type='text'>
This patch adds board support for the Toradex Apalis TK1 a computer on
module which can be used on different carrier boards.

The module consists of a Tegra TK1 SoC, a PMIC solution, 2 GB of DDR3L
RAM, a bunch of level shifters, an eMMC, a TMP451 temperature sensor
chip, an I210 gigabit Ethernet controller and a SGTL5000 audio codec.
Furthermore, there is a Kinetis MK20DN512 companion micro controller for
analogue, CAN and resistive touch functionality.

For the sake of ease of use we do not distinguish between different
carrier boards for now as the base module features are deemed
sufficient enough for regular booting.

The following functionality is working so far:
- eMMC boot, environment storage and Toradex factory config block
- Gigabit Ethernet
- MMC/SD cards (both MMC1 as well as SD1 slot)
- USB client/host (dual role OTG port as client e.g. for DFU/UMS or host,
  other two ports as host)

Signed-off-by: Marcel Ziswiler &lt;marcel.ziswiler@toradex.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Marcel Ziswiler &lt;marcel@ziswiler.com&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
</entry>
<entry>
<title>arcv2: Halt non-master cores</title>
<updated>2017-03-31T19:09:36Z</updated>
<author>
<name>Alexey Brodkin</name>
<email>abrodkin@synopsys.com</email>
</author>
<published>2017-03-30T14:50:45Z</published>
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<id>urn:sha1:6cba327bd96f90818a8beede51405228c54a5251</id>
<content type='text'>
Even though we expect only master core to execute U-Boot code
let's make sure even if for some reason slave cores attempt to
execute U-Boot in parallel with master they get halted very early.

If platform wants it may kick-start slave cores before passing control
to say Linux kernel or any other application that want to see all cores
of SMP SoC up and running.

Signed-off-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
</content>
</entry>
<entry>
<title>arm64: mvebu: armada-7040-db.dts: Change eth1 speed from 2.5G to 1G</title>
<updated>2017-03-29T05:44:43Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2017-03-09T13:35:28Z</published>
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<id>urn:sha1:d74238aeb671f45929086be0a91fb6583d11924a</id>
<content type='text'>
The default configuration for the COMPHY-0 port should be 1G, as its
used as 1G SGMII connection. This change is necessary to get the
MAC2 port (SGMII) working on this DB.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Stefan Chulski &lt;stefanc@marvell.com&gt;
Cc: Kostya Porotchkin &lt;kostap@marvell.com&gt;
Cc: Nadav Haklai &lt;nadavh@marvell.com&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
<entry>
<title>arm64: marvell: dts: add PPv2.2 description to Armada 7K/8K</title>
<updated>2017-03-29T05:42:25Z</updated>
<author>
<name>Thomas Petazzoni</name>
<email>thomas.petazzoni@free-electrons.com</email>
</author>
<published>2017-02-20T11:27:25Z</published>
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<id>urn:sha1:a6555ebe1bd8bde87c7baccd83ce127bb1a6f098</id>
<content type='text'>
This commit adds the description of the PPv2.2 hardware block for the
Marvell Armada 7K and Armada 8K processors, and their corresponding Armada
7040 and 8040 Development boards.

Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
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