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<title>u-boot.git/arch, branch v2018.01-rc1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>Merge git://git.denx.de/u-boot-uniphier</title>
<updated>2017-12-04T15:24:35+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-12-04T15:24:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0c4d24823ed28c94dae56a10a66687c69b70c1d1'/>
<id>0c4d24823ed28c94dae56a10a66687c69b70c1d1</id>
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<pre>
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</entry>
<entry>
<title>arm: Make gcc 6.0 or later a hard requirement now.</title>
<updated>2017-12-04T15:23:53+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2017-12-03T01:11:31+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6b867dabe84bae1e74e88f4af620c26cb793c4c2'/>
<id>6b867dabe84bae1e74e88f4af620c26cb793c4c2</id>
<content type='text'>
Move the warning to an error as we have been promising would happen in
this release.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
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<pre>
Move the warning to an error as we have been promising would happen in
this release.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>armv8: mmu: fix page table mapping</title>
<updated>2017-12-04T15:23:52+00:00</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2017-11-28T02:31:28+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=90351547ceeb76c1337757c51af0fb5a2c30bd02'/>
<id>90351547ceeb76c1337757c51af0fb5a2c30bd02</id>
<content type='text'>
To page mapping the lowest 2 bits needs to be 0x3.
If not fix this, the final lowest 3 bits for page mapping is 0x1
which is marked as reserved.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
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<pre>
To page mapping the lowest 2 bits needs to be 0x3.
If not fix this, the final lowest 3 bits for page mapping is 0x1
which is marked as reserved.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64 :show_regs: show the address before relocation</title>
<updated>2017-12-04T15:23:52+00:00</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2017-11-28T02:08:08+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=082693f4f02ad7a9de192e73feae34e28856b8e3'/>
<id>082693f4f02ad7a9de192e73feae34e28856b8e3</id>
<content type='text'>
After relocation, when error happends, it is hard to track
ELR and LR with asm file objdumped from elf file.

So subtract the gd-&gt;reloc_off the reflect the compliation address.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
After relocation, when error happends, it is hard to track
ELR and LR with asm file objdumped from elf file.

So subtract the gd-&gt;reloc_off the reflect the compliation address.

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: arch-meson: build memory banks using reported memory from registers</title>
<updated>2017-12-04T15:17:29+00:00</updated>
<author>
<name>Neil Armstrong</name>
<email>narmstrong@baylibre.com</email>
</author>
<published>2017-11-27T09:35:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c7be3e5a796a7b5c92035013d89e8182c7aab6bb'/>
<id>c7be3e5a796a7b5c92035013d89e8182c7aab6bb</id>
<content type='text'>
As discussed at [1], the Amlogic Meson GX SoCs can embed a BL31 firmware
and a secondary BL32 firmware.
Since mid-2017, the reserved memory address of the BL31 firmware was moved
and grown for security reasons.

But mainline U-Boot and Linux has the old address and size fixed.

These SoCs have a register interface to get the two firmware reserved
memory start and sizes.

This patch adds a dynamic reservation of the memory zones in the device tree bootmem
reserved memory zone used by the kernel in early boot.
To be complete, the memory zones are also added to the EFI reserved zones.

Depends on patchset "Add support for Amlogic GXL Based SBCs" at [2].

[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-October/004860.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005410.html

Changes since v1:
- switched the #if to if(IS_ENABLED()) to compile all code paths
- renamed function to meson_board_add_reserved_memory()
- added a mem.h header with comment
- updated all boards ft_board_setup()

Changes since RFC v2:
- reduced preprocessor load
- kept Odroid-C2 static memory mapping as exception

Changes since RFC v1:
- switch to fdt rsv mem table and efi reserve memory
- replaced in_le32 by readl()

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
[trini: Fix warning on khadas-vim over missing &lt;asm/arch/mem.h&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<pre>
As discussed at [1], the Amlogic Meson GX SoCs can embed a BL31 firmware
and a secondary BL32 firmware.
Since mid-2017, the reserved memory address of the BL31 firmware was moved
and grown for security reasons.

But mainline U-Boot and Linux has the old address and size fixed.

These SoCs have a register interface to get the two firmware reserved
memory start and sizes.

This patch adds a dynamic reservation of the memory zones in the device tree bootmem
reserved memory zone used by the kernel in early boot.
To be complete, the memory zones are also added to the EFI reserved zones.

Depends on patchset "Add support for Amlogic GXL Based SBCs" at [2].

[1] http://lists.infradead.org/pipermail/linux-amlogic/2017-October/004860.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005410.html

Changes since v1:
- switched the #if to if(IS_ENABLED()) to compile all code paths
- renamed function to meson_board_add_reserved_memory()
- added a mem.h header with comment
- updated all boards ft_board_setup()

Changes since RFC v2:
- reduced preprocessor load
- kept Odroid-C2 static memory mapping as exception

Changes since RFC v1:
- switch to fdt rsv mem table and efi reserve memory
- replaced in_le32 by readl()

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
[trini: Fix warning on khadas-vim over missing &lt;asm/arch/mem.h&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: Add Khadas VIM support based on Meson GXL family</title>
<updated>2017-12-04T14:59:03+00:00</updated>
<author>
<name>Neil Armstrong</name>
<email>narmstrong@baylibre.com</email>
</author>
<published>2017-11-27T09:16:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5ff2ee44ee7d09c99bdf1be7349c1212149c573c'/>
<id>5ff2ee44ee7d09c99bdf1be7349c1212149c573c</id>
<content type='text'>
This adds platform code for the Khadas VIM board based on a
Meson GXL (S905X) SoC with the Meson GXL configuration.

This initial submission supports UART, MMC/SDCard and Ethernet with the
Internal RMII PHY.

The meson-gxl-s905x-khadas-vim.dts is synchronised from the linux 4.13
stable tree as of 4.13.8.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</content>
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<pre>
This adds platform code for the Khadas VIM board based on a
Meson GXL (S905X) SoC with the Meson GXL configuration.

This initial submission supports UART, MMC/SDCard and Ethernet with the
Internal RMII PHY.

The meson-gxl-s905x-khadas-vim.dts is synchronised from the linux 4.13
stable tree as of 4.13.8.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: Add LibreTech CC support based on Meson GXL family</title>
<updated>2017-12-04T14:59:03+00:00</updated>
<author>
<name>Neil Armstrong</name>
<email>narmstrong@baylibre.com</email>
</author>
<published>2017-11-27T09:16:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=96e7b5a174365c87adabbafed56f2258de04b207'/>
<id>96e7b5a174365c87adabbafed56f2258de04b207</id>
<content type='text'>
This adds platform code for the Libre Computer CC "Le Potato" board based on a
Meson GXL (S905X) SoC with the Meson GXL configuration.

This initial submission supports UART, MMC/SDCard and Ethernet with the
Internal RMII PHY.

The meson-gxl-s905x-libretech-cc.dts is synchronised from the linux 4.13
stable tree as of 4.13.8.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This adds platform code for the Libre Computer CC "Le Potato" board based on a
Meson GXL (S905X) SoC with the Meson GXL configuration.

This initial submission supports UART, MMC/SDCard and Ethernet with the
Internal RMII PHY.

The meson-gxl-s905x-libretech-cc.dts is synchronised from the linux 4.13
stable tree as of 4.13.8.

Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: arch-meson: add ethernet common init function</title>
<updated>2017-12-04T14:59:02+00:00</updated>
<author>
<name>Neil Armstrong</name>
<email>narmstrong@baylibre.com</email>
</author>
<published>2017-11-27T09:16:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6915b1033105b23ebc725be772bec00838830667'/>
<id>6915b1033105b23ebc725be772bec00838830667</id>
<content type='text'>
Introduce a generic common Ethernet Hardware init function
common to all Amlogic GX SoCs with support for the
Internal PHY enable for GXL SoCs.

Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Introduce a generic common Ethernet Hardware init function
common to all Amlogic GX SoCs with support for the
Internal PHY enable for GXL SoCs.

Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>armv8: shrink exception table code</title>
<updated>2017-12-04T14:59:02+00:00</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2017-11-27T00:47:09+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=78ad457b2dbd0fe6cdc7ea42a69774a72ed007b9'/>
<id>78ad457b2dbd0fe6cdc7ea42a69774a72ed007b9</id>
<content type='text'>
In the moment our exception entry code needs 34 instructions, so we
can't use put it directly into the table entry, which offers "only"
32 instructions there. Right now we just put an unconditional branch
there, then use a macro to place the 34 instructions *per entry* after
that. That effectivly doubles the size of our exception table, which
is quite a waste, given that we use it mostly for debugging purposes.

Since the register saving part is actually identical, let's just convert
that macro into a function, and "bl" into it directly from the exception
slot, of course after having saved at least the original LR.
This saves us about 950 bytes of code, which is quite a relief for some
tight SPLs, in particular the 64-bit Allwinner ones.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
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<pre>
In the moment our exception entry code needs 34 instructions, so we
can't use put it directly into the table entry, which offers "only"
32 instructions there. Right now we just put an unconditional branch
there, then use a macro to place the 34 instructions *per entry* after
that. That effectivly doubles the size of our exception table, which
is quite a waste, given that we use it mostly for debugging purposes.

Since the register saving part is actually identical, let's just convert
that macro into a function, and "bl" into it directly from the exception
slot, of course after having saved at least the original LR.
This saves us about 950 bytes of code, which is quite a relief for some
tight SPLs, in particular the 64-bit Allwinner ones.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>add support for Raspberry Pi Zero W</title>
<updated>2017-12-04T14:59:02+00:00</updated>
<author>
<name>Dmitry Korunov</name>
<email>dessel.k@gmail.com</email>
</author>
<published>2017-11-26T09:38:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8993056fb3d4af4f0cd078df20130d4e7c35c2f7'/>
<id>8993056fb3d4af4f0cd078df20130d4e7c35c2f7</id>
<content type='text'>
Signed-off-by: Dmitry Korunov &lt;dessel.k@gmail.com&gt;
</content>
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<pre>
Signed-off-by: Dmitry Korunov &lt;dessel.k@gmail.com&gt;
</pre>
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</content>
</entry>
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