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<title>u-boot.git/arch, branch v2018.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-sunxi</title>
<updated>2018-07-04T03:09:34+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-07-04T03:09:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4ac5df4b41ba46d7e635bdd8d500721c642b0a0d'/>
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<pre>
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<entry>
<title>arm: timer: sunxi: add Allwinner timer erratum workaround</title>
<updated>2018-07-03T16:30:00+00:00</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2018-06-27T00:42:53+00:00</published>
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The Allwinner A64 SoCs suffers from an arch timer implementation erratum,
where sometimes the lower 11 bits of the counter value erroneously
become all 0's or all 1's [1]. This leads to sudden jumps, both forwards and
backwards, with the latter one often showing weird behaviour.
Port the workaround proposed for Linux to U-Boot and activate it for all
A64 boards.
This fixes crashes when accessing MMC devices (SD cards), caused by a
recent change to actually use the counter value for timeout checks.

Fixes: 5ff8e54888e4d26a352453564f7f599d29696dc9 ("sunxi: improve throughput
in the sunxi_mmc driver")

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/576886.html

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Tested-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Tested-by: Andreas Färber &lt;afaerber@suse.de&gt;
Tested-by: Guillaume Gardet &lt;guillaume.gardet@free.fr&gt;
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The Allwinner A64 SoCs suffers from an arch timer implementation erratum,
where sometimes the lower 11 bits of the counter value erroneously
become all 0's or all 1's [1]. This leads to sudden jumps, both forwards and
backwards, with the latter one often showing weird behaviour.
Port the workaround proposed for Linux to U-Boot and activate it for all
A64 boards.
This fixes crashes when accessing MMC devices (SD cards), caused by a
recent change to actually use the counter value for timeout checks.

Fixes: 5ff8e54888e4d26a352453564f7f599d29696dc9 ("sunxi: improve throughput
in the sunxi_mmc driver")

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/576886.html

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Tested-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Tested-by: Andreas Färber &lt;afaerber@suse.de&gt;
Tested-by: Guillaume Gardet &lt;guillaume.gardet@free.fr&gt;
</pre>
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</entry>
<entry>
<title>arm: timer: factor out FSL arch timer erratum workaround</title>
<updated>2018-07-03T16:29:46+00:00</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2018-06-27T00:42:52+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=38651588d3d9a977ca457049d6357408ddad4a8b'/>
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At the moment we have the workaround for the Freescale arch timer
erratum A-008585 merged into the generic timer_read_counter() routine.
Split those two up, so that we can add other errata workaround more
easily. Also add an explaining comment on the way.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Tested-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Tested-by: Andreas Färber &lt;afaerber@suse.de&gt;
Tested-by: Guillaume Gardet &lt;guillaume.gardet@free.fr&gt;
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<pre>
At the moment we have the workaround for the Freescale arch timer
erratum A-008585 merged into the generic timer_read_counter() routine.
Split those two up, so that we can add other errata workaround more
easily. Also add an explaining comment on the way.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Tested-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Tested-by: Andreas Färber &lt;afaerber@suse.de&gt;
Tested-by: Guillaume Gardet &lt;guillaume.gardet@free.fr&gt;
</pre>
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</content>
</entry>
<entry>
<title>board/aries: Remove</title>
<updated>2018-07-02T19:52:50+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-07-02T19:52:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=03b54997d568a6879a045ba775e44d62289a8fb9'/>
<id>03b54997d568a6879a045ba775e44d62289a8fb9</id>
<content type='text'>
The various Aries Embedded boards have been orphaned for a year and no
one has come forward to take care of them.  Remove.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
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The various Aries Embedded boards have been orphaned for a year and no
one has come forward to take care of them.  Remove.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
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</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-x86</title>
<updated>2018-07-02T02:13:34+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-07-02T02:13:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ac378bb05fa3cac3197085431f577e0dbddd4b4a'/>
<id>ac378bb05fa3cac3197085431f577e0dbddd4b4a</id>
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</entry>
<entry>
<title>x86: efi_loader: Build EFI memory map per E820 table</title>
<updated>2018-07-02T01:23:28+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2018-06-28T03:38:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=abe47ca728f5b22d1ec9fcf609e00b331c4d5273'/>
<id>abe47ca728f5b22d1ec9fcf609e00b331c4d5273</id>
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On x86 traditional E820 table is used to pass the memory information
to kernel. With EFI loader we can build the EFI memory map from it.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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On x86 traditional E820 table is used to pass the memory information
to kernel. With EFI loader we can build the EFI memory map from it.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>x86: Use microcode update from device tree for all processors</title>
<updated>2018-07-02T01:23:28+00:00</updated>
<author>
<name>Ivan Gorinov</name>
<email>ivan.gorinov@intel.com</email>
</author>
<published>2018-06-22T04:16:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8199a145c40791f0bc272fc016494028cf250195'/>
<id>8199a145c40791f0bc272fc016494028cf250195</id>
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Built without a ROM image with FSP (u-boot.rom), the U-Boot loader applies
the microcode update data block encoded in Device Tree to the bootstrap
processor but not passed to the other CPUs when multiprocessing is enabled.

If the bootstrap processor successfully performs a microcode update
from Device Tree, use the same data block for the other processors.

Signed-off-by: Ivan Gorinov &lt;ivan.gorinov@intel.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
[bmeng: fixed build errors on edison and qemu-x86]
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
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Built without a ROM image with FSP (u-boot.rom), the U-Boot loader applies
the microcode update data block encoded in Device Tree to the bootstrap
processor but not passed to the other CPUs when multiprocessing is enabled.

If the bootstrap processor successfully performs a microcode update
from Device Tree, use the same data block for the other processors.

Signed-off-by: Ivan Gorinov &lt;ivan.gorinov@intel.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
[bmeng: fixed build errors on edison and qemu-x86]
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>x86: Add scsi command to coreboot and qemu</title>
<updated>2018-07-02T01:23:28+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2018-06-26T10:58:55+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fc48ebe6dff059a799c8f85e31ee8dea6c2f77d8'/>
<id>fc48ebe6dff059a799c8f85e31ee8dea6c2f77d8</id>
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This adds the scsi command to coreboot and qemu, to be in consistent
with other x86 targets.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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This adds the scsi command to coreboot and qemu, to be in consistent
with other x86 targets.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-usb</title>
<updated>2018-06-30T12:52:06+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-06-30T12:52:06+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3fcb00be25b0a810c76dac4ed368a57b5c8e75b2'/>
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<pre>
</pre>
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</entry>
<entry>
<title>mx5: Select ARM_CORTEX_A8_CVE_2017_5715</title>
<updated>2018-06-30T12:49:55+00:00</updated>
<author>
<name>Fabio Estevam</name>
<email>fabio.estevam@nxp.com</email>
</author>
<published>2018-06-20T18:08:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ee322f3c79a86e6f26629f8535cddb2b844d5113'/>
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On a 4.18-rc1 kernel the following warning is seen on i.MX51 and
i.MX53:

CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable

Select the ARM_CORTEX_A8_CVE_2017_5715 workaround for i.MX51/i.MX53
to fix the problem.

With this patch applied the kernel reports:

CPU0: Spectre v2: using BPIALL workaround

Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
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On a 4.18-rc1 kernel the following warning is seen on i.MX51 and
i.MX53:

CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable

Select the ARM_CORTEX_A8_CVE_2017_5715 workaround for i.MX51/i.MX53
to fix the problem.

With this patch applied the kernel reports:

CPU0: Spectre v2: using BPIALL workaround

Signed-off-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
</pre>
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