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<title>u-boot.git/arch, branch v2018.11</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>imx: mkimage: add size check to the u-boot.imx make target</title>
<updated>2018-11-12T10:08:53+00:00</updated>
<author>
<name>Marcel Ziswiler</name>
<email>marcel.ziswiler@toradex.com</email>
</author>
<published>2018-11-09T14:31:17+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=43e6f94cbcaf193aeedcf86e85a3ff4c79f66773'/>
<id>43e6f94cbcaf193aeedcf86e85a3ff4c79f66773</id>
<content type='text'>
The make macro to check if the binary exceeds the board size limit is
taken straight from the root Makefile.

Without this and e.g. enabled EFI Vybrid fails booting as the regular
size limit check does not take the final u-boot.imx binary size into
account which is bigger due to alignment as well as IMX header stuff.

Signed-off-by: Marcel Ziswiler &lt;marcel.ziswiler@toradex.com&gt;
Reviewed-by: Fabio Estevam &lt;festevam@gmail.com&gt;
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<pre>
The make macro to check if the binary exceeds the board size limit is
taken straight from the root Makefile.

Without this and e.g. enabled EFI Vybrid fails booting as the regular
size limit check does not take the final u-boot.imx binary size into
account which is bigger due to alignment as well as IMX header stuff.

Signed-off-by: Marcel Ziswiler &lt;marcel.ziswiler@toradex.com&gt;
Reviewed-by: Fabio Estevam &lt;festevam@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>imx: imx6: perform gpr_init only on suitable cpu types</title>
<updated>2018-11-08T13:35:40+00:00</updated>
<author>
<name>Christoph Niedermaier</name>
<email>cniedermaier@dh-electronics.de</email>
</author>
<published>2018-10-19T15:40:54+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=19bbd098254fefd94199001e721f92f167f7ed9e'/>
<id>19bbd098254fefd94199001e721f92f167f7ed9e</id>
<content type='text'>
If the function gpr_init is used in a common MX6 spl
implementation we have to ensure that it is only called for
suitable cpu types, otherwise it breaks hardware parts like
enet1, can1, can2, etc.

Signed-off-by: Christoph Niedermaier &lt;cniedermaier@dh-electronics.de&gt;
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<pre>
If the function gpr_init is used in a common MX6 spl
implementation we have to ensure that it is only called for
suitable cpu types, otherwise it breaks hardware parts like
enet1, can1, can2, etc.

Signed-off-by: Christoph Niedermaier &lt;cniedermaier@dh-electronics.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-imx-20181106' of git://git.denx.de/u-boot-imx</title>
<updated>2018-11-06T16:12:00+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-11-06T16:12:00+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=dd610e616cceda16a81dfa6f9a134877f783548c'/>
<id>dd610e616cceda16a81dfa6f9a134877f783548c</id>
<content type='text'>
Fix coverity issues for i.MX8
</content>
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<pre>
Fix coverity issues for i.MX8
</pre>
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</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-marvell</title>
<updated>2018-11-06T15:37:31+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-11-06T15:37:31+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=acf52fb26fe527e8ba2643017e3d747686a4c40e'/>
<id>acf52fb26fe527e8ba2643017e3d747686a4c40e</id>
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<pre>
</pre>
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</entry>
<entry>
<title>arm: mvebu: armada-xp-theadorable.dts: Change CS# for 2nd FPGA</title>
<updated>2018-11-06T12:21:13+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2018-10-23T10:25:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ae4c38a5384033c7f5584e33cce1adc511fff333'/>
<id>ae4c38a5384033c7f5584e33cce1adc511fff333</id>
<content type='text'>
The new board version has the 2nd FPGA connected via CS# 0 instead of
2 on SPI bus 1. Change this setup in the DT accordingly. Please note
that this change does still work on the old board version because the
CS signal is not used on this board.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
The new board version has the 2nd FPGA connected via CS# 0 instead of
2 on SPI bus 1. Change this setup in the DT accordingly. Please note
that this change does still work on the old board version because the
CS signal is not used on this board.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: mvebu: armada-xp-theadorable.dts: Add "spi-flash" compatible property</title>
<updated>2018-11-06T12:21:13+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2018-10-23T10:25:15+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6843db99224e1e94ef7ef4c1d7bce5615cd3589d'/>
<id>6843db99224e1e94ef7ef4c1d7bce5615cd3589d</id>
<content type='text'>
Add the "spi-flash" compatible string so that the generic sf_probe
driver can probe the SPI flash on the theadorable Armada-XP board.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
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<pre>
Add the "spi-flash" compatible string so that the generic sf_probe
driver can probe the SPI flash on the theadorable Armada-XP board.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: mvebu: Move PCI(e) MBUS window to end of RAM</title>
<updated>2018-11-06T12:21:13+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2018-10-22T12:21:17+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a8483505e88e9e90bf4e166093dca5f99acbe2b2'/>
<id>a8483505e88e9e90bf4e166093dca5f99acbe2b2</id>
<content type='text'>
With patch 49b23e035d96 (pci: mvebu: Increase size of PCIe default mapping)
the mapping size for each PCI(e) controller was increased from 32MiB to
128MiB. This leads to problems on boards with multiple PCIe slots / ports
which are unable to map all PCIe ports, e.g. the Armada-XP theadorable:

DRAM:  2 GiB (667 MHz, 64-bit, ECC not enabled)
SF: Detected m25p128 with page size 256 Bytes, erase size 256 KiB, total 16 MiB
Cannot add window '4:f8', conflicts with another window
PCIe unable to add mbus window for mem at f0000000+08000000
Model: Marvell Armada XP theadorable

This patch moves the base address for the PCI(e) memory spaces from
0xe8000000 to the end of SDRAM (clipped to a max of 0xc0000000 right now).
This gives move room and flexibility for PCI(e) mappings.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: VlaoMao &lt;vlaomao@gmail.com&gt;
Tested-by: VlaoMao &lt;vlaomao at gmail.com&gt;
</content>
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<pre>
With patch 49b23e035d96 (pci: mvebu: Increase size of PCIe default mapping)
the mapping size for each PCI(e) controller was increased from 32MiB to
128MiB. This leads to problems on boards with multiple PCIe slots / ports
which are unable to map all PCIe ports, e.g. the Armada-XP theadorable:

DRAM:  2 GiB (667 MHz, 64-bit, ECC not enabled)
SF: Detected m25p128 with page size 256 Bytes, erase size 256 KiB, total 16 MiB
Cannot add window '4:f8', conflicts with another window
PCIe unable to add mbus window for mem at f0000000+08000000
Model: Marvell Armada XP theadorable

This patch moves the base address for the PCI(e) memory spaces from
0xe8000000 to the end of SDRAM (clipped to a max of 0xc0000000 right now).
This gives move room and flexibility for PCI(e) mappings.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: VlaoMao &lt;vlaomao@gmail.com&gt;
Tested-by: VlaoMao &lt;vlaomao at gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: dts: fsl-imx8qxp-mek: Move regulator outside "simple-bus"</title>
<updated>2018-11-06T10:25:55+00:00</updated>
<author>
<name>Fabio Estevam</name>
<email>festevam@gmail.com</email>
</author>
<published>2018-10-26T00:49:31+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=78c640fed6a4b2cccc74ca052fb8a2193499ac56'/>
<id>78c640fed6a4b2cccc74ca052fb8a2193499ac56</id>
<content type='text'>
Commit 3c28576bb0f0 ("arm: dts: imx8qxp: fix build warining")
fixed the dts warning by removing the unnecessary
#address-cells/#size-cells, but the recommendation for regulators is not
to place them under "simple-bus", so move the reg_usdhc2_vmmc regulator
accordingly.

Signed-off-by: Fabio Estevam &lt;festevam@gmail.com&gt;
</content>
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<pre>
Commit 3c28576bb0f0 ("arm: dts: imx8qxp: fix build warining")
fixed the dts warning by removing the unnecessary
#address-cells/#size-cells, but the recommendation for regulators is not
to place them under "simple-bus", so move the reg_usdhc2_vmmc regulator
accordingly.

Signed-off-by: Fabio Estevam &lt;festevam@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: acpi: Remove redundant Offset (0x00)</title>
<updated>2018-11-06T05:35:06+00:00</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2018-10-31T17:14:08+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=24109bba6a4f81774e384c15c2e8a4d47791455f'/>
<id>24109bba6a4f81774e384c15c2e8a4d47791455f</id>
<content type='text'>
New ACPI assembler issues a warning:

board/intel/edison/dsdt.asl.tmp     13:     Offset (0x00),
Remark   2158 -                                       ^ Unnecessary/redundant use of Offset operator

Indeed, in the OperationRegion the offset is 0x00 by default.

Thus, drop unneeded Offset() use as suggested by ACPI assembler.

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
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<pre>
New ACPI assembler issues a warning:

board/intel/edison/dsdt.asl.tmp     13:     Offset (0x00),
Remark   2158 -                                       ^ Unnecessary/redundant use of Offset operator

Indeed, in the OperationRegion the offset is 0x00 by default.

Thus, drop unneeded Offset() use as suggested by ACPI assembler.

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-sh</title>
<updated>2018-11-04T13:12:21+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-11-04T13:12:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5ef76e59c12c79d106ebda70b710468aa6bd8b75'/>
<id>5ef76e59c12c79d106ebda70b710468aa6bd8b75</id>
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<pre>
</pre>
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</content>
</entry>
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