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<title>u-boot.git/arch, branch v2018.11-rc3</title>
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<updated>2018-10-29T15:21:00Z</updated>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-sunxi</title>
<updated>2018-10-29T15:21:00Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-10-29T15:21:00Z</published>
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<id>urn:sha1:2f07a9a6d1abd1eeb283a21a8d718dc9628429a4</id>
<content type='text'>
</content>
</entry>
<entry>
<title>sunxi: store DRAM size in SPL header</title>
<updated>2018-10-29T15:11:15Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2018-10-25T09:23:07Z</published>
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<id>urn:sha1:5776610e9ef022e2d8a15793d4b9955c3f8076ed</id>
<content type='text'>
At the moment we rely on the infamous get_ram_size() function to learn
the actual DRAM size in U-Boot proper. This function has two issues:
1) It only works if the DRAM size is a power of two. We start to see
boards which have 3GB of (usable) DRAM, so this does not fit anymore.
2) As U-Boot has no notion of reserved memory so far, it will happily
ride through the DRAM, possibly stepping on secure-only memory. This
could be a region of DRAM reserved for OP-TEE or some other secure
payload, for instance. It will most likely crash in that case.

As the SPL DRAM init routine has very accurate knowledge of the actual
DRAM size, lets propagate this wisdom to U-Boot proper.
We re-purpose a currently reserved word in our SPL header for that.
The SPL itself stores the detected DRAM size there, and bumps the SPL
header version number in that case. U-Boot proper checks for a valid
SPL header and a high enough version number, then uses the DRAM size
from there. If the SPL header field is not sufficient, we fall back to
the old DRAM scanning routine.

Part of the DRAM might be present and probed by SPL, but not accessible
by the CPU. They're restricted in the main U-Boot binary, when accessing
the DRAM size from SPL header.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: Icenowy Zheng &lt;icenowy@aosc.io&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
</content>
</entry>
<entry>
<title>sunxi: add Kconfig option for the maximum accessible DRAM</title>
<updated>2018-10-29T15:11:15Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>icenowy@aosc.io</email>
</author>
<published>2018-10-25T09:23:06Z</published>
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<id>urn:sha1:f8aa3f8d84af6e9ae0dce9c3577d342c6a013b14</id>
<content type='text'>
Allwinner 64-bit SoCs can use 4GiB DRAM chip, however their memory map
has only allocated 3GiB for DRAM, so only 3GiB of the DRAM is
accessible.

Add a Kconfig option for the maximum accessible DRAM.

For A80 it should be a much higher value (8GiB), but as I have no A80
device to test and originally U-Boot only supports 2GiB DRAM on A80, it
currently still falls under the 2GiB situation.

Signed-off-by: Icenowy Zheng &lt;icenowy@aosc.io&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
</content>
</entry>
<entry>
<title>sunxi: map DRAM part with 3G size</title>
<updated>2018-10-29T15:11:15Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>icenowy@aosc.io</email>
</author>
<published>2018-10-25T09:23:05Z</published>
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<id>urn:sha1:7009134c99512bd8a9a09cf14f35450f32a8602c</id>
<content type='text'>
All Allwinner 64-bit SoCs now are known to be able to access 3GiB of
external DRAM, however the size of DRAM part in the MMU translation
table is still 2GiB.

Change the size of DRAM part in MMU table to 3GiB.

Signed-off-by: Icenowy Zheng &lt;icenowy@aosc.io&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
</content>
</entry>
<entry>
<title>sunxi: Extend SPL header versioning</title>
<updated>2018-10-29T15:11:15Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2018-10-25T09:23:03Z</published>
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<id>urn:sha1:55d481d2014f79a692ac82a10a439dc71acc732c</id>
<content type='text'>
On Allwinner SoCs we use some free bytes at the beginning of the SPL image
to store various information. We have a version byte to allow updates,
but changing this always requires all tools to be updated as well.

Introduce the concept of semantic versioning [1] to the SPL header:
The major part of the version number only changes on incompatible
updates, a minor number bump indicates backward compatibility.
This patch just documents the major/minor split, adds some comments
to the header file and uses the versioning information for the existing
users.

[1] https://semver.org

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Signed-off-by: Icenowy Zheng &lt;icenowy@aosc.io&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
Acked-by: Jagan Teki &lt;jagan@openedev.com&gt;
</content>
</entry>
<entry>
<title>sunxi: disable Pine A64 model detection code on other boards</title>
<updated>2018-10-29T15:11:07Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>icenowy@aosc.io</email>
</author>
<published>2018-10-25T09:23:02Z</published>
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<id>urn:sha1:c6c2c85e4b980cba54b34a55399f9b82ae2787ea</id>
<content type='text'>
The Pine A64 Plus/non-Plus model detection code is now built on all
64-bit ARM SoCs, even if the code cannot be triggered when H5/H6 is in
use.

Disable them when the board is Pine A64 by adding a Kconfig option that
is only selected on Pine A64.

On GCC 7.3.1 this makes the size of the function reduces 184 bytes, and
saves a 104 byte strstr() function, then makes SPL on H6 succeed to
build.

Signed-off-by: Icenowy Zheng &lt;icenowy@aosc.io&gt;
Reviewed-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
Reviewed-by: Jagan Teki &lt;jagan@openedev.com&gt;
</content>
</entry>
<entry>
<title>x86: Fix car_uninit weak symbol definition</title>
<updated>2018-10-28T13:02:15Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2018-10-25T10:05:37Z</published>
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<id>urn:sha1:3d2be8003c77cad350f1ec7c79f914797718c5bf</id>
<content type='text'>
Since commit 80df194f0165 ("x86: detect unsupported relocation types"),
an error message is seen on QEMU x86 target during boot:

do_elf_reloc_fixups32: unsupported relocation type 0x1 at fff841f0, offset = 0xfff00087
do_elf_reloc_fixups32: unsupported relocation type 0x2 at fff841f8, offset = 0xfff00091

Check offset 0xfff00087 and 0xfff00091 in the u-boot ELF image,

fff00087  000df401 R_386_32          00000000   car_uninit
fff00091  000df402 R_386_PC32        00000000   car_uninit

we see R_386_32 and R_386_PC32 relocation type is generated for
symbol car_uninit, which is declared as a weak symbol in start.S.

However the actual weak symbol implementation ends up nowhere. As
we can see below, it's *UND*.

$ objdump -t u-boot | grep car_uninit
00000000  w      *UND*  00000000 car_uninit

With this fix, it is normal now.

$ objdump -t u-boot | grep car_uninit
fff00094  w    F .text.start    00000001 car_uninit

Reported-by: Hannes Schmelzer &lt;hannes@schmelzer.or.at&gt;
Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Tested-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Reviewed-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Tested-by: Hannes Schmelzer &lt;oe5hpm@oevsv.at&gt;
</content>
</entry>
<entry>
<title>x86: BayTrail: southcluster.asl: Change PCI 64 bit address range / region</title>
<updated>2018-10-28T13:02:15Z</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2018-10-22T12:07:53Z</published>
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<id>urn:sha1:7d2a0534a6a4a4b92a58098f484f9e172149b784</id>
<content type='text'>
To allow bigger 64 bit prefetchable PCI regions in Linux, this patch
changes the base address and range of the ACPI area passed to Linux.
BayTrail can only physically access 36 bit of PCI address space. So
just chaning the range without changing the base address won't work
here, as 0xf.ffff.ffff is already the maximum address.

With this patch, a maximum of 16 GiB of local DDR is supported. This
should be enough for all BayTrail boards though.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-imx-20181025' of git://git.denx.de/u-boot-imx</title>
<updated>2018-10-25T14:16:21Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-10-25T14:16:21Z</published>
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<id>urn:sha1:cf033e04da315ba949e804c127abae0134bda30f</id>
<content type='text'>
Merged imx8 architecture, fix build for imx8 + warnings
</content>
</entry>
<entry>
<title>arm: dts: imx8qxp: fix build warining</title>
<updated>2018-10-25T09:48:13Z</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2018-10-25T08:36:49Z</published>
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<id>urn:sha1:3c28576bb0f0990d699fd330089412e620706941</id>
<content type='text'>
Fix below build warning.

arch/arm/dts/fsl-imx8qxp-mek.dtb: Warning (avoid_unnecessary_addr_size):
/regulators: unnecessary #address-cells/#size-cells without "ranges"
or child "reg" property

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
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