u-boot.git/arch, branch v2020.01-rc1 Unnamed repository; edit this file 'description' to name the repository. Merge branch '2019-10-28-azure-ci-support' 2019-10-30T13:05:13+00:00 Tom Rini trini@konsulko.com 2019-10-30T13:05:13+00:00 ba742b839c524f7723799d750a540ad3fe70ca7f - Clean up Travis-CI slightly and then add support for Microsoft Azure pipelines, all from Bin Meng. 
- Clean up Travis-CI slightly and then add support for Microsoft Azure
  pipelines, all from Bin Meng.
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi 2019-10-30T13:04:52+00:00 Tom Rini trini@konsulko.com 2019-10-30T13:04:52+00:00 cc64810dc6234a3537502a05988fa7a1a6fa5d55 - H6 dts(i) sync (Clément) - H6 PIO (Icenowy) - Fix pll1 clock calculation (Stefan) - H6 dram, half DQ (Jernej) - A64 OLinuXino eMMC (Sunil) 
- H6 dts(i) sync (Clément)
- H6 PIO (Icenowy)
- Fix pll1 clock calculation (Stefan)
- H6 dram, half DQ (Jernej)
- A64 OLinuXino eMMC (Sunil)
arm: mvebu: Avoid generating kwbimage.cfg in the source tree 2019-10-29T20:17:36+00:00 Bin Meng bmeng.cn@gmail.com 2019-10-28T14:25:01+00:00 6cdd177ca9092d1ee094dd3709e25d116e329ca0 At present some boards generate kwbimage.cfg in the source tree during the build. This breaks buildman testing on some systems where the source tree is read-only. Update makefile rules to generate it in the build tree instead. Note some other boards have the kwbimage.cfg file written in advance, hence we need check if the file exists in the build tree first, otherwise we fall back to one in the source tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> 
At present some boards generate kwbimage.cfg in the source tree
during the build. This breaks buildman testing on some systems
where the source tree is read-only. Update makefile rules to
generate it in the build tree instead.

Note some other boards have the kwbimage.cfg file written in
advance, hence we need check if the file exists in the build
tree first, otherwise we fall back to one in the source tree.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mips 2019-10-26T00:07:24+00:00 Tom Rini trini@konsulko.com 2019-10-26T00:07:24+00:00 ffc379b42c85466e1dd4c8fee8268801f26d2ab8 - bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs - bmips: various small fixes - mtmips: add new drivers for clock, reset-controller and pinctrl - mtmips: add support for high speed UART - mtmips: update/enhance drivers for SPI and ethernet - mtmips: add support for MMC 
- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC
Merge branch '2019-10-24-ti-imports' 2019-10-25T21:33:28+00:00 Tom Rini trini@konsulko.com 2019-10-25T21:33:28+00:00 15147dc6a96697880cf355ed9df127bd8c896f2c - Enable DFU on dra7xx boards - Further Keystone 3 platform improvements 
- Enable DFU on dra7xx boards
- Further Keystone 3 platform improvements
arm: dts: k3-am65: Add R5F ranges in interconnect nodes 2019-10-25T21:33:21+00:00 Suman Anna s-anna@ti.com 2019-10-17T03:33:08+00:00 d0e134b909f75db080c9364bfb84d6bf1d724844 Add the address spaces for the R5F cores in MCU domain to the ranges property of the cbass_mcu interconnect node so that the addresses within the R5F nodes can be translated properly by the relevant OF address API. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> 
Add the address spaces for the R5F cores in MCU domain to the ranges
property of the cbass_mcu interconnect node so that the addresses
within the R5F nodes can be translated properly by the relevant OF
address API.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
armv7R: K3: j721e: Add support for triggering ddr init from SPL 2019-10-25T21:33:21+00:00 Lokesh Vutla lokeshvutla@ti.com 2019-10-07T13:56:38+00:00 22b548044b840d67bd941c5b66602ae643db21d3 In SPL, DDR should be made available by the end of board_init_f() so that apis in board_init_r() can use ddr. Adding support for triggering DDR initialization from board_init_f(). Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> 
In SPL, DDR should be made available by the end of board_init_f()
so that apis in board_init_r() can use ddr. Adding support for
triggering DDR initialization from board_init_f().

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arm: dts: k3-j721e: Add ddr node 2019-10-25T21:33:21+00:00 Lokesh Vutla lokeshvutla@ti.com 2019-10-07T13:56:37+00:00 ec2fa9f76e892b9fd38fe39c564bf9348ab135bd Use the 3733MTs DDR configuration that is auto generated from DDR_Regconfig tool. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Kevin Scholz <k-scholz@ti.com> 
Use the 3733MTs DDR configuration that is auto generated from
DDR_Regconfig tool.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Kevin Scholz <k-scholz@ti.com>
ram: k3-am654: Do not rely on default values for certain DDR register 2019-10-25T21:33:21+00:00 James Doublesin doublesin@ti.com 2019-10-07T08:34:27+00:00 34f27b2e86b996483be30d05e3c753a4fc055adf Added the following registers to the DDR configuration: - ACIOCR0, - ACIOCR3, - V2H_CTL_REG, - DX8SLxDQSCTL. Modified enable_dqs_pd and disable_dqs_pd to only touch the associated bit fields for pullup and pulldown registers (to preserve slew rate and other bits in that same register). Also update the dts files in the same patch to maintain git bisectability. Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> 
Added the following registers to the DDR configuration:
- ACIOCR0,
- ACIOCR3,
- V2H_CTL_REG,
- DX8SLxDQSCTL.

Modified enable_dqs_pd and disable_dqs_pd to only touch the associated
bit fields for pullup and pulldown registers (to preserve slew rate and
other bits in that same register). Also update the dts files in the same
patch to maintain git bisectability.

Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
armv7r: dts: am654-base-board: Rename 1600MHz to 1600MTs in dtsi filename 2019-10-25T21:33:21+00:00 James Doublesin doublesin@ti.com 2019-10-07T08:34:25+00:00 d5e08fd2042975fb60d807aed477d5b8c6e8cf16 The current configuration of DDR on AM654 base board is for 1600MTs but the file name is specified as k3-am654-base-board-ddr4-1600MHz.dtsi. Since 1600MHz is misleading, rename it to k3-am654-base-board-ddr4-1600MTs.dtsi Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> 
The current configuration of DDR on AM654 base board is for 1600MTs but
the file name is specified as k3-am654-base-board-ddr4-1600MHz.dtsi.
Since 1600MHz is misleading, rename it to
k3-am654-base-board-ddr4-1600MTs.dtsi

Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>