u-boot.git/arch, branch v2020.01-rc5

dts: am335x-brsmarc1/xre1: insert phy_id again

2019-12-13T18:01:12Z

commit 3b3e8a37d36e ("arm: dts: am335x: sync cpsw/mdio/phy with latest linux - drop phy_id") did sync with recent linux kernel and replaced therefore the 'phy_id' property with a phy-handle pointing to the mdio. This is OK for linux, but introduces trouble with the already running vxWorks on this target. So this commit here re-inerts the phy_id property beside the phy-handle property to be compatible with both. Signed-off-by: Hannes Schmelzer

Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv

2019-12-10T02:53:23Z

- Increase stack size to avoid a stack overflow during distro boot. - Add hifive-unleashed-a00.dts for SIFIVE FU540. - Add OF_SEPARATE support for SIFIVE FU540. - Add SPL support for Andes AX25 AE350. - Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.

riscv: add option to wait for ack from secondary harts in smp functions

2019-12-10T00:23:10Z

Add a wait option to smp_call_function() to wait for the secondary harts to acknowledge the call-function request. The request is considered to be acknowledged once each secondary hart has cleared the corresponding IPI. As part of the call-function request, the secondary harts invalidate the instruction cache after clearing the IPI. This adds a delay between acknowledgment (clear IPI) and fulfillment (call function) of the request. We want to use the acknowledgment to be able to judge when the request has been completed. Remove the delay by clearing the IPI after cache invalidation and just before calling the function from the request. Signed-off-by: Lukas Auer Reviewed-by: Rick Chen Tested-by: Rick Chen Reviewed-by: Anup Patel

riscv: add functions for reading the IPI status

2019-12-10T00:23:10Z

Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer Reviewed-by: Rick Chen

riscv: dts: Add #address-cells and #size-cells in nor node

2019-12-10T00:23:10Z

Those are required for cfi-flash driver to get correct address information. Also modify size description correctly. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao

riscv: dts: Support four cores SMP

2019-12-10T00:23:10Z

Add CPU2 and CPU3 information in cpus node to support four cores SMP booting. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao

riscv: Fix clear bss loop in the start-up code

2019-12-10T00:23:10Z

For RV64, it will use sd instruction to clear t0 register, and the increament will be 8 bytes. So if the difference between__bss_strat and __bss_end was not 8 bytes aligned, the clear bss loop will overflow and acks like system hang. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao

riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL

2019-12-10T00:23:10Z

The mcache_ctl csr only can be manipulated in M mode. Add SPL_RISCV_MMODE for U-Boot SPL to control cache operation. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao

riscv: andes_plic: Fix some wrong configurations

2019-12-10T00:23:10Z

Fix two wrong settings of andes plic driver as below: 1. Fix wrong pending register base definition. 2. Declaring the en variable in enable_ipi() as unsigned int instead of int can help to fix wrong plic enabling setting in RV64. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao

riscv: ax25: add SPL support

2019-12-10T00:23:10Z

The U-Boot SPL will boot in M mode and load the FIT image which include OpenSBI and U-Boot proper images. After loading progress, it will jump to OpenSBI first and then U-Boot proper which will run in S mode. Also remove V5L2_CACHE due to U-Boot SPL code size consideration. Without this concern, it can be enable manually for performance. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao