u-boot.git/arch, branch v2020.07-rc3 Unnamed repository; edit this file 'description' to name the repository. Merge tag 'ti-v2020.07-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti 2020-05-25T18:09:42+00:00 Tom Rini trini@konsulko.com 2020-05-25T18:09:42+00:00 60c7facfc965af6ff8ea14ee26c9d49cd2d0ec22 - Enable DM_ETH on omap3_logic board - Enable Caches in SPL for K3 platforms - Enable backup boot mode support for J721E - Update the DDR timings for AM654 EVM - Add automated tests for RX-51 
- Enable DM_ETH on omap3_logic board
- Enable Caches in SPL for K3 platforms
- Enable backup boot mode support for J721E
- Update the DDR timings for AM654 EVM
- Add automated tests for RX-51
sandbox: move compression option to Kconfig 2020-05-25T15:54:53+00:00 Michael Walle michael@walle.cc 2020-05-22T12:07:38+00:00 efc0644802a2c9c1747539e017562aabde1f54ec CONFIG_BZIP2 and CONFIG_GZIP_COMPRESSED are Kconfig options. Select them by CONFIG_SANDBOX instead of setting them in configs/sandbox.h. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Simon Glass <sjg@chromium.org> 
CONFIG_BZIP2 and CONFIG_GZIP_COMPRESSED are Kconfig options. Select them
by CONFIG_SANDBOX instead of setting them in configs/sandbox.h.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
armv8: cache_v8: fix mmu_set_region_dcache_behaviour 2020-05-25T15:54:53+00:00 Peng Fan peng.fan@nxp.com 2020-05-11T08:41:07+00:00 b4b26192112bd2c225b8e424c2e2d360761cd864 The enum dcache_optoion contains a shift left 2 bits in the armv8 case already. The PMD_ATTRINDX(option) macro will perform a left shift of 2 bits. Perform a right shift so that in the end we get the correct value. [trini: Reword the commit message] Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> 
The enum dcache_optoion contains a shift left 2 bits in the armv8 case
already.  The PMD_ATTRINDX(option) macro will perform a left shift of 2
bits.  Perform a right shift so that in the end we get the correct
value.

[trini: Reword the commit message]
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Merge git://git.denx.de/u-boot-usb 2020-05-23T02:58:50+00:00 Tom Rini trini@konsulko.com 2020-05-23T02:58:50+00:00 9c5fef577494769e3ff07952a85f9b7125ef765b - DM support for OMAP - DWC3 fix - Typo fix in eth/r8152 
- DM support for OMAP
- DWC3 fix
- Typo fix in eth/r8152
Merge tag 'u-boot-rockchip-20200522' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip 2020-05-22T14:28:38+00:00 Tom Rini trini@konsulko.com 2020-05-22T14:28:38+00:00 f53c2dc162d0c62debd0ebb88383e3b6fee95c10 - Fix rk3288 chromebook veyron support; - Add pcie driver support for rk3399; - other fixes for rk3399 boards 
- Fix rk3288 chromebook veyron support;
- Add pcie driver support for rk3399;
- other fixes for rk3399 boards
usb: ehci-omap: Add Support for DM_USB and OF_CONTROL 2020-05-22T13:22:35+00:00 Adam Ford aford173@gmail.com 2020-05-16T06:19:53+00:00 94ed66194f150c308d1713965a28abce3ac6e200 The omap3.dtsi file shows the usbhshost node with two sub-nodes for ohci and ehci. This patch file creates the usbhshost, and pulls the portX-mode information. It then locates the EHCI sub-node, and initializes the EHCI controller with the info pulled from the usbhshost node. There is still more to do since there isn't an actual link between the 'phys' reference and the corresponding phy driver, and there is no nop-xceiv driver yet. In the meantime, the older style reference to CONFIG_OMAP_EHCI_PHYx_RESET_GPIO is still needed to pull the phy out of reset until the phy driver is completed and the phandle reference is made. Signed-off-by: Adam Ford <aford173@gmail.com> 
The omap3.dtsi file shows the usbhshost node with two sub-nodes
for ohci and ehci.  This patch file creates the usbhshost, and
pulls the portX-mode information.  It then locates the EHCI
sub-node, and initializes the EHCI controller with the info
pulled from the usbhshost node.

There is still more to do since there isn't an actual link
between the 'phys' reference and the corresponding phy driver,
and there is no nop-xceiv driver yet.

In the meantime, the older style reference to
CONFIG_OMAP_EHCI_PHYx_RESET_GPIO is still needed to pull
the phy out of reset until the phy driver is completed and the
phandle reference is made.

Signed-off-by: Adam Ford <aford173@gmail.com>
rockchip: rk3328: rock64 - fix gen3 SPL hang 2020-05-22T12:53:20+00:00 Kurt Miller kurt@intricatesoftware.com 2020-05-13T19:55:20+00:00 33863f744d513f5c16a254870e7b3cef8580bbc9 Use the same approach as ROC-RK3328-CC which enables SPL GPIO, pinctl and regulator support. This allows the gen3 board to boot through SPL and does not break gen2 in the process. Signed-off-by: Kurt Miller <kurt@intricatesoftware.com> Acked-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
Use the same approach as ROC-RK3328-CC which enables SPL GPIO,
pinctl and regulator support. This allows the gen3 board to
boot through SPL and does not break gen2 in the process.

Signed-off-by: Kurt Miller <kurt@intricatesoftware.com>
Acked-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rockchip: spl-boot-order: do not attempt to access fdt if OF_PLATDATA 2020-05-22T12:53:20+00:00 Urja Rannikko urjaman@gmail.com 2020-05-13T19:15:22+00:00 e68a84360173f90fa37df875e6aa2c83f2858b80 gd->fdt_blob is null if using OF_PLATDATA in SPL, which causes a hang after f0921f5098 ("fdt: Sync up to the latest libfdt"). We use the same test that is used in spl_common_init on whether to call fdtdec_setup to unconditionally avoid linking in the fdt-using code when not necessary and thus reduce SPL size. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
gd->fdt_blob is null if using OF_PLATDATA in SPL, which causes a hang
after f0921f5098 ("fdt: Sync up to the latest libfdt").
We use the same test that is used in spl_common_init on whether to call
fdtdec_setup to unconditionally avoid linking in the fdt-using code
when not necessary and thus reduce SPL size.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rockchip: spl: veyron speedy boots from SPI 2020-05-22T12:53:20+00:00 Urja Rannikko urjaman@gmail.com 2020-05-13T19:15:20+00:00 353ad95aa6562654726a91cb457f30d5f2a85f4c Apparently speedy was forgotten from this list of veyron devices. Fixes: 49105fb7ed ("rockchip: add common spl board file") Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
Apparently speedy was forgotten from this list of veyron devices.

Fixes: 49105fb7ed ("rockchip: add common spl board file")
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rockchip: Enable PCIe/M.2 on rk3399 board w/ M.2 2020-05-22T12:53:20+00:00 Jagan Teki jagan@amarulasolutions.com 2020-05-09T16:56:23+00:00 765a12d6a39ee2151421c5fc0250d9eefdf0e085 Enable PCIe/M.2 support on - NanoPC-T4 - ROC-RK3399-PC Mezzanine boards. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
Enable PCIe/M.2 support on
- NanoPC-T4
- ROC-RK3399-PC Mezzanine boards.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>