u-boot.git/arch, branch v2020.10-rc5

x86: acpi: Add memset to initialize SPCR table

2020-09-21T08:41:36Z

Add a missing memset to acpi_create_spcr(). The other acpi_create_xxxx() functions perform a memset on their structures, acpi_create_spcr() does not and as a result the contents of this table are partly uninitialized (and thus random after every reset). Fixes: b288cd960072 ("x86: acpi: Generate SPCR table") Signed-off-by: Wolfgang Wallner Reviewed-by: Andy Shevchenko Reviewed-by: Simon Glass Reviewed-by: Bin Meng [bmeng: fix the tags format in the commit message] Signed-off-by: Bin Meng

x86: acpi: Fix calculation of DSDT length

2020-09-21T08:41:35Z

Currently, the calculation for the length of the DSDT table includes any bytes that are added for alignment, but those bytes are not initialized. This is because the DSDT length is calculated after a call to acpi_inc_align(). Split this up into the following sequence: * acpi_inc() * Calculate DSDT length * acpi_align() Signed-off-by: Wolfgang Wallner Reviewed-by: Andy Shevchenko Reviewed-by: Simon Glass Reviewed-by: Bin Meng

x86: fsp: Replace e-mmc with emmc in devicetree bindings

2020-09-21T08:41:35Z

The term eMMC is used inconsistently within the FSP devicetree bindings (e-mmc and emmc), especially for "emmc-host-max-speed" documentation and code disagree. Change all eMMC instances within the FSP bindings to consistently use "emmc". The term "emmc" is already used a lot within U-Boot, while "e-mmc" is only used in the FSP bindings. Signed-off-by: Wolfgang Wallner Reviewed-by: Simon Glass Reviewed-by: Bin Meng [bmeng: correct one typo in the commit message] Signed-off-by: Bin Meng

apalis-imx8qm: rename all occurences to apalis-imx8

2020-09-17T12:41:33Z

The Toradex product is called apalis-imx8 consisting of SoM with i.MX8QM and i.MX8QP SoCs. Signed-off-by: Philippe Schenker Reviewed-by: Igor Opaniuk

colibri-imx8qxp: rename all occurences to colibri-imx8x

2020-09-17T12:41:26Z

The Toradex product is called colibri-imx8x consisting of SoM with i.MX8QXP and i.MX8DX SoCs. Signed-off-by: Philippe Schenker Reviewed-by: Igor Opaniuk

ARM: mx6: ddr: Add support for iMX6UL/ULL/SL/SDL

2020-09-17T12:40:55Z

This patch adds support for iMX6UL/ULL/SL/SDL MMDC into the DDR calibration code. The difference between MX6DQ and MX6UL/ULL/SL is that the later SoCs have 2 SDQS registers, just like MX6SX, while the MX6DQ/MX6SDL has 8. Fixes: 4f4c128c65 ("ARM: mx6: ddr: Add support for iMX6SX") Signed-off-by: Marek Vasut Cc: Eric Nelson Cc: Fabio Estevam Cc: Stefano Babic Reviewed-by: Fabio Estevam

imx8mp: Remove parts MIMX8ML7 and MIMX8ML5 support

2020-09-17T12:40:22Z

Latest datasheet revE has removed MIMX8ML7D/5D/7C/5C parts, so update u-boot to remove decoding and support for those parts. Signed-off-by: Ye Li Signed-off-by: Peng Fan

imx8m: clock_imx8mm: add missed return

2020-09-17T12:40:17Z

Add missed return Signed-off-by: Peng Fan

imx8mq: fix SSCG_PLL_REFCLK_SEL_x

2020-09-17T12:40:10Z

Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16 Reported-by: Coverity 3448860 Signed-off-by: Peng Fan Reviewed-by: Ye Li

imx8mq: fix FRAC_PLL_REFCLK_SEL_MASK

2020-09-17T12:40:04Z

Coverity reported dead code, however it is FRAC_PLL_REFCLK_SEL_MASK was wrongly set. Reported-by: Coverity 10045172 Signed-off-by: Peng Fan Reviewed-by: Ye Li