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<title>u-boot.git/arch, branch v2022.01-rc4</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/arch?h=v2022.01-rc4</id>
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<updated>2021-12-17T04:58:01Z</updated>
<entry>
<title>arm: socfpga: arria10: Enable double peripheral RBF configuration</title>
<updated>2021-12-17T04:58:01Z</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2021-11-07T15:08:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4720b83d2c711062cfb55f03591b8f12c897d7cb'/>
<id>urn:sha1:4720b83d2c711062cfb55f03591b8f12c897d7cb</id>
<content type='text'>
Double peripheral RBF configuration are needed on some devices or boards
to stabilize the IO configuration system.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
Signed-off-by: Sin Hui Kho &lt;sin.hui.kho@intel.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: arria10: Reset MPFE NoC after program periph / combined RBF</title>
<updated>2021-12-17T04:58:01Z</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2021-11-07T15:08:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3b4ee40f20eb7bb687a4429546fd3cd3073b90d2'/>
<id>urn:sha1:3b4ee40f20eb7bb687a4429546fd3cd3073b90d2</id>
<content type='text'>
This patch triggers warm reset to recover the MPFE NoC from corruption
due to high frequency transient clock output from HPS EMIF IOPLL at
VCO startup after peripheral RBF is programmed.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
Signed-off-by: Sin Hui Kho &lt;sin.hui.kho@intel.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: arria10: Setting image magic value to romcode initswstate reg</title>
<updated>2021-12-17T04:58:01Z</updated>
<author>
<name>Tien Fong Chee</name>
<email>tien.fong.chee@intel.com</email>
</author>
<published>2021-11-07T15:08:54Z</published>
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<id>urn:sha1:2f27754eb7f5321b9e4ff80870f03e35357a02a5</id>
<content type='text'>
The romcode_initswstate register need to be set with FSBL_IMAGE_IS_VALID
value if the current FSBL image is found valid, otherwise BootROM will
look for next subsequent valid FSBL image when warm reset is triggered.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
Signed-off-by: Sin Hui Kho &lt;sin.hui.kho@intel.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-stm32-20211213' of https://source.denx.de/u-boot/custodians/u-boot-stm</title>
<updated>2021-12-13T15:20:25Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2021-12-13T15:20:25Z</published>
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<id>urn:sha1:cfbd2bc695b87434e52e1b1073756b823f18f09d</id>
<content type='text'>
- enable KSZ90x1 PHY driver on DHCOR
- DHSOM boards:
  - increase USB power-good delay
  - add update_sf script to install U-Boot into SF
  - increase PHY auto-negotiation timeout to 20 seconds
  - fix SoM and board coding strap GPIO handling

# gpg verification failed.
</content>
</entry>
<entry>
<title>ARM: dts: stm32: Add custom PHY reset bindings on AV96</title>
<updated>2021-12-13T13:34:11Z</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2021-11-13T02:27:37Z</published>
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<id>urn:sha1:98fe251a241ce98860b8d3075331d081de0a166a</id>
<content type='text'>
The ethernet PHY must be reset on AV96, however DWMAC currently does
not support the MDIO-bus PHY GPIO reset bindings and the ethernet MAC
PHY reset property is going away on next DT sync. Add PHY specific
reset bindings to trigger the PHY reset and fix sporadic ethernet
malfunctions, until the next DT sync.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
Cc: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Reviewed-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
</content>
</entry>
<entry>
<title>arm: dts: Create common rz-g2-beacon-u-boot file</title>
<updated>2021-12-12T23:37:28Z</updated>
<author>
<name>Adam Ford</name>
<email>aford173@gmail.com</email>
</author>
<published>2021-12-06T16:29:28Z</published>
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<id>urn:sha1:61b3a0101acd5d1c08348fca85ac4c075be3f607</id>
<content type='text'>
The rzg2_beacon_defconfig creates an image for RZ/G2[MNH] and
as such creates three different device trees and each of them
have a corresponding -u-boot.dtsi file which are basically
copies of each other.  Create a common include file to be
referenced by each of the respective board-u-boot.dtsi files
to reduce duplicate code and simplify support going forward.
This also restores some lost functionality from the device
tree re-sync and updates the MAINTAINER file to include all
beacon-renesom device tree files.

Signed-off-by: Adam Ford &lt;aford173@gmail.com&gt;
</content>
</entry>
<entry>
<title>arm: dts: beacon-rzg2: Resync device trees with Linux 5.16-rc3</title>
<updated>2021-12-12T23:37:28Z</updated>
<author>
<name>Adam Ford</name>
<email>aford173@gmail.com</email>
</author>
<published>2021-12-06T16:29:27Z</published>
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<id>urn:sha1:1eaf61c84db6100585fea4be20dbf8748c728685</id>
<content type='text'>
The device trees for the Beacon RZ/G2[MNH] boards have undergone
some changes over time, so resync them now.

Signed-off-by: Adam Ford &lt;aford173@gmail.com&gt;
</content>
</entry>
<entry>
<title>efi: Add uclass for devices provided by UEFI firmware</title>
<updated>2021-12-09T19:43:25Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-12-04T15:56:31Z</published>
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<id>urn:sha1:42b7f4212a1cb9aa6a5ca959d1f40b6f8465fd8c</id>
<content type='text'>
UCLASS_EFI_LOADER is used for devices created by applications and
drivers loaded by U-Boots UEFI implementation.

This patch provides a new uclass (UCLASS_EFI_MEDIA) to be used for devices
that provided by a UEFI firmware calling U-Boot as an EFI application.

If the two uclasses can be unified, is left to future redesign.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
</content>
</entry>
<entry>
<title>sunxi: dts: Fix typoed eMMC check</title>
<updated>2021-12-08T23:06:56Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2021-11-30T23:18:54Z</published>
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<id>urn:sha1:e32dad292ae1422eba1403964918eed220061769</id>
<content type='text'>
Commit 03510bf62149 ("sunxi: only include alias for eMMC when mmc2
used") protected the eMMC alias in U-Boot's DT stub the with the
associated Kconfig symbol, but was actually using the wrong name.

Fix the name of the symbol to match what's defined in Kconfig and what
the defconfig files actually use.

Fixes: 03510bf62149 ("sunxi: only include alias for eMMC when mmc2 used")
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
Reported-by: 5kft@5kft.org
Reviewed-by: Icenowy Zheng &lt;icenowy@aosc.io&gt;
</content>
</entry>
<entry>
<title>riscv: Enable SPI flash env for SiFive Unmatched.</title>
<updated>2021-12-02T08:43:56Z</updated>
<author>
<name>Thomas Skibo</name>
<email>thomas-git@skibo.net</email>
</author>
<published>2021-11-24T22:32:10Z</published>
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<id>urn:sha1:c0ffc12a701621dc72dfc896965cbfe5b0dbf9b4</id>
<content type='text'>
Enable saving environment to SPI flash memory on SiFive
Unmatched.

Signed-off-by: Thomas Skibo &lt;thomas-git@skibo.net&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
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