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<title>u-boot.git/arch, branch v2022.04-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
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<updated>2022-02-14T18:04:39Z</updated>
<entry>
<title>arm: pdu001: Fix dt to work with the current am33xx dtsi files</title>
<updated>2022-02-14T18:04:39Z</updated>
<author>
<name>Felix Brack</name>
<email>fb@ltec.ch</email>
</author>
<published>2022-02-08T10:38:39Z</published>
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<id>urn:sha1:9f0deae6d5fa656d604b3efa2371ea52def22173</id>
<content type='text'>
The changes introduced with commit 6337d53fdf45 ("arm: dts: sync am33xx
with Linux 5.9-rc7") prevent the PDU001 from operating correctly.
This patch fixes the configuration of the pin multiplexer and uart3.

Signed-off-by: Felix Brack &lt;fb@ltec.ch&gt;
</content>
</entry>
<entry>
<title>acpi: Move acpi_write_tables() to a generic header</title>
<updated>2022-02-11T16:29:23Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2022-01-29T21:30:52Z</published>
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<id>urn:sha1:aafb31fc953aac0af89e44a1e4a841803141768d</id>
<content type='text'>
This function is used by both x86 and sandbox. Put it in a common header
file.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>arm:dts:k3-am64-sk: EMIF tool update to 0.8.0 with 1333MTs for lpddr4</title>
<updated>2022-02-10T22:17:39Z</updated>
<author>
<name>Sinthu Raja</name>
<email>sinthu.raja@ti.com</email>
</author>
<published>2021-11-29T12:04:49Z</published>
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<id>urn:sha1:ad41ed120893522e23cc24550bb2d1dfb745a075</id>
<content type='text'>
EMIF tool for AM64 SK is now updated to 0.8.0 that includes
* disabled Write DQ training
* improve CA ODT to 60 ohms

The lpddr4 enabled with periodic WDQ training is causing periodic 26us
stall. This makes the SoC stall without doing anything which leads to
R5 interrupt latency in TCM memory. Due to this periodic training there
are some outstanding CPU transactions waiting for the lpddr4 to complete.

Hence, disable the periodic write DQ training during the
non-initialization stage of lpddr4 which results in an approximate 1us
stall. Also, update the lpddr4 config to improve CA ODT by 60 ohms

The rationales are as follows:
- PI_WDQLVL_EN: 2 Bits register field to support write DQ leveling,
  disable bit 1 that supports Write DQ during non-initialization to
  avoid ~26us stall during code execution.

- MR11_DATA_F1/F2_x register fields value changed to 0x66 that changes
  the CA ODT from 48ohm to 60ohm to improve the eye margin on CA bus by
  increasing the signal swing.

Signed-off-by: James Doublesin &lt;doublesin@ti.com&gt;
Signed-off-by: Sinthu Raja &lt;sinthu.raja@ti.com&gt;
</content>
</entry>
<entry>
<title>powerpc: mpc8xx: drop CONFIG_SYS_RESET_ADDRESS</title>
<updated>2022-02-10T21:44:23Z</updated>
<author>
<name>Ovidiu Panait</name>
<email>ovidiu.panait@windriver.com</email>
</author>
<published>2022-01-31T07:20:21Z</published>
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<id>urn:sha1:6303b275a3424dc1b6c79e98ac575ab2c88659eb</id>
<content type='text'>
There are no boards that define CONFIG_SYS_RESET_ADDRESS, so drop the
associated mpc8xx code that checks for it.

Signed-off-by: Ovidiu Panait &lt;ovidiu.panait@windriver.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Acked-by: Christophe Leroy &lt;christophe.leroy@csgroup.eu&gt;
</content>
</entry>
<entry>
<title>spi: apple: Add driver for Apple SPI controller</title>
<updated>2022-02-10T21:44:23Z</updated>
<author>
<name>Mark Kettenis</name>
<email>kettenis@openbsd.org</email>
</author>
<published>2022-01-23T15:48:12Z</published>
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<id>urn:sha1:7184e2997e7d97ba3e697a0acc1800ddd89d3f6d</id>
<content type='text'>
Add a driver for the SPI controller integrated on Apple SoCs.
This is necessary to support the keyboard on Apple Silicon laopts
since their keyboard uses an Apple-specific HID over SPI protocol.

Signed-off-by: Mark Kettenis &lt;kettenis@openbsd.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested on: Macbook Air M1
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>power: domain: apple: Add reset support</title>
<updated>2022-02-10T21:44:23Z</updated>
<author>
<name>Mark Kettenis</name>
<email>kettenis@openbsd.org</email>
</author>
<published>2022-01-22T19:38:17Z</published>
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<id>urn:sha1:81fafbbeba3211ed60ac8aff41a2e1fcb9a40431</id>
<content type='text'>
The power management controller found on Apple SoCs als provides
a way to reset all devices within a power domain. This is needed
to cleanly shutdown the NVMe controller before we hand over
control to the OS.

Signed-off-by: Mark Kettenis &lt;kettenis@openbsd.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested on: Macbook Air M1
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
</content>
</entry>
<entry>
<title>arm: apple: Add RTKit support</title>
<updated>2022-02-10T21:44:23Z</updated>
<author>
<name>Mark Kettenis</name>
<email>kettenis@openbsd.org</email>
</author>
<published>2022-01-22T19:38:14Z</published>
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<id>urn:sha1:02e2588d3f8fed7bf25ac1677072dd607c4dd72e</id>
<content type='text'>
Most Apple IOPs run a firmware that is based on what Apple calls
RTKit. RTKit implements a common mailbox protocol.  This code
provides an implementation of the AP side of this protocol,
providing a function to initialize RTKit-based firmwares as well
as a function to do a clean shutdown of this firmware.

Signed-off-by: Mark Kettenis &lt;kettenis@openbsd.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested on: Macbook Air M1
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>arm: apple: Change SoC name from "m1" into "apple"</title>
<updated>2022-02-10T21:44:23Z</updated>
<author>
<name>Mark Kettenis</name>
<email>kettenis@openbsd.org</email>
</author>
<published>2022-01-22T19:38:13Z</published>
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<id>urn:sha1:a4bd5e4120d6389476c078076ce2746e3058037a</id>
<content type='text'>
U-Boot is expected to support multiple generations of Apple SoCs
in a single binary with a single defconfig. Therefore it makes
more sense to set SYS_SOC to "apple".

Signed-off-by: Mark Kettenis &lt;kettenis@openbsd.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>mailbox: apple: Add driver for Apple IOP mailbox</title>
<updated>2022-02-10T21:44:23Z</updated>
<author>
<name>Mark Kettenis</name>
<email>kettenis@openbsd.org</email>
</author>
<published>2022-01-22T19:38:12Z</published>
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<id>urn:sha1:456305ec597908536e8e0de32dade43f9db00e8c</id>
<content type='text'>
This mailbox driver provides a communication channel with the
Apple IOP controllers found on Apple SoCs.  These IOP controllers
are used to implement various functions such as the System
Manegement Controller (SMC) and NVMe storage.  It allows sending
and receiving a 96-bit message over a single channel.

The header file with the struct used for mailbox messages is taken
straight from Linux.

Signed-off-by: Mark Kettenis &lt;kettenis@openbsd.org&gt;
Signed-off-by: Sven Peter &lt;sven@svenpeter.dev&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested on: Macbook Air M1
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>acpi: Move MCFG implementation to common lib</title>
<updated>2022-02-09T19:30:13Z</updated>
<author>
<name>Moritz Fischer</name>
<email>moritzf@google.com</email>
</author>
<published>2022-02-05T20:17:45Z</published>
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<id>urn:sha1:058fb9f5ffc422f987c33adb01f8fa6e4434eff8</id>
<content type='text'>
MCFG tables are used on multiple arches. Move to common ACPI lib.

Cc: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Moritz Fischer &lt;moritzf@google.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Use sizeof(*mcfg) instead of sizeof(*header)
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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