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<title>u-boot.git/arch, branch v2022.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<entry>
<title>Merge commit 'ef5ba2cef4a08b68caaa9215fcac142d3025bbf7' of https://github.com/tienfong/uboot_mainline</title>
<updated>2022-07-01T13:14:32+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-07-01T13:14:32+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9fcc2fb3fec3f2f09594747e4c47f3758f79b9df'/>
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<entry>
<title>Merge tag 'u-boot-amlogic-20220701' of https://source.denx.de/u-boot/custodians/u-boot-amlogic</title>
<updated>2022-07-01T13:13:58+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-07-01T13:13:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=085fea0b65c0aab6962e4e62c0fd376e3c63a90e'/>
<id>085fea0b65c0aab6962e4e62c0fd376e3c63a90e</id>
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- search dtb for meson-axg-usb-ctrl on board axg
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- search dtb for meson-axg-usb-ctrl on board axg
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<entry>
<title>socfpga: arria10: Allow dcache_enable before relocation</title>
<updated>2022-07-01T06:57:15+00:00</updated>
<author>
<name>Paweł Anikiel</name>
<email>pan@semihalf.com</email>
</author>
<published>2022-06-17T10:47:26+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e26ecebc684bfe74f6c27cca151c3490d1ed5d8f'/>
<id>e26ecebc684bfe74f6c27cca151c3490d1ed5d8f</id>
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Before relocating to SDRAM, the ECC is initialized by clearing the
whole SDRAM. In order to speed this up, dcache_enable is used (see
sdram_init_ecc_bits).

Since commit 503eea451903 ("arm: cp15: update DACR value to activate
access control"), this no longer works, because running code in OCRAM
with the XN bit set causes a page fault. Override dram_bank_mmu_setup
to disable XN in the OCRAM and setup DRAM dcache before relocation.

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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Before relocating to SDRAM, the ECC is initialized by clearing the
whole SDRAM. In order to speed this up, dcache_enable is used (see
sdram_init_ecc_bits).

Since commit 503eea451903 ("arm: cp15: update DACR value to activate
access control"), this no longer works, because running code in OCRAM
with the XN bit set causes a page fault. Override dram_bank_mmu_setup
to disable XN in the OCRAM and setup DRAM dcache before relocation.

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
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</entry>
<entry>
<title>socfpga: arria10: Replace delays with busy waiting in cm_full_cfg</title>
<updated>2022-07-01T06:57:14+00:00</updated>
<author>
<name>Paweł Anikiel</name>
<email>pan@semihalf.com</email>
</author>
<published>2022-06-17T10:47:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=aea0e80a9feff740a6cb6323c67452bc5a752e4d'/>
<id>aea0e80a9feff740a6cb6323c67452bc5a752e4d</id>
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Using udelay while the clocks aren't fully configured causes the timer
system to save the wrong clock rate. Use sdelay and wait_on_value
instead (the values used in these functions were found experimentally).

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
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Using udelay while the clocks aren't fully configured causes the timer
system to save the wrong clock rate. Use sdelay and wait_on_value
instead (the values used in these functions were found experimentally).

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</pre>
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</entry>
<entry>
<title>config: Add Chameleonv3 config</title>
<updated>2022-07-01T06:57:14+00:00</updated>
<author>
<name>Paweł Anikiel</name>
<email>pan@semihalf.com</email>
</author>
<published>2022-06-17T10:47:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=61298270c56d14f55e26ac17c8b5e110aa13e12c'/>
<id>61298270c56d14f55e26ac17c8b5e110aa13e12c</id>
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Add defconfig and Kconfig files for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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Add defconfig and Kconfig files for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
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</entry>
<entry>
<title>arm: dts: Add Chameleonv3 devicetrees</title>
<updated>2022-07-01T06:57:14+00:00</updated>
<author>
<name>Paweł Anikiel</name>
<email>pan@semihalf.com</email>
</author>
<published>2022-06-17T10:47:18+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8566b3682fe5ef7d6f67432de98f3e583e2b830c'/>
<id>8566b3682fe5ef7d6f67432de98f3e583e2b830c</id>
<content type='text'>
Add devicetrees for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Signed-off-by: Alexandru M Stan &lt;amstan@chromium.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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Add devicetrees for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Signed-off-by: Alexandru M Stan &lt;amstan@chromium.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>arm: dts: Add Chameleonv3 handoff headers</title>
<updated>2022-07-01T06:57:14+00:00</updated>
<author>
<name>Paweł Anikiel</name>
<email>pan@semihalf.com</email>
</author>
<published>2022-06-17T10:47:17+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=882c00edeb994e0e27540f332a7fe7ceb20d0c34'/>
<id>882c00edeb994e0e27540f332a7fe7ceb20d0c34</id>
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Add handoff headers for the Google Chameleonv3 variants: 480-2 and
270-3. Both files were generated using qts-filter-a10.sh.

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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Add handoff headers for the Google Chameleonv3 variants: 480-2 and
270-3. Both files were generated using qts-filter-a10.sh.

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: dts: Add Mercury+ AA1 devicetrees</title>
<updated>2022-07-01T06:57:13+00:00</updated>
<author>
<name>Paweł Anikiel</name>
<email>pan@semihalf.com</email>
</author>
<published>2022-06-17T10:47:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e21b8ac3f16faf3343f13d5832735bbaacb99df2'/>
<id>e21b8ac3f16faf3343f13d5832735bbaacb99df2</id>
<content type='text'>
Devicetree headers for Mercury+ AA1 module

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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Devicetree headers for Mercury+ AA1 module

Signed-off-by: Paweł Anikiel &lt;pan@semihalf.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: pinebook-pro: sync PBP dtb to 5.18</title>
<updated>2022-06-29T03:43:05+00:00</updated>
<author>
<name>Peter Robinson</name>
<email>pbrobinson@gmail.com</email>
</author>
<published>2022-06-12T14:25:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fce1e9bba263fb5e3e589fdc5c2321f733e3de81'/>
<id>fce1e9bba263fb5e3e589fdc5c2321f733e3de81</id>
<content type='text'>
Sync the pinebook pro to upstream 5.18, in particular this brings
brings in a fix so the DP is disabled so Linux will actually boot.

Signed-off-by: Peter Robinson &lt;pbrobinson@gmail.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
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Sync the pinebook pro to upstream 5.18, in particular this brings
brings in a fix so the DP is disabled so Linux will actually boot.

Signed-off-by: Peter Robinson &lt;pbrobinson@gmail.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: Add option to prevent booting on power plug-in</title>
<updated>2022-06-29T03:42:10+00:00</updated>
<author>
<name>Chris Morgan</name>
<email>macromorgan@hotmail.com</email>
</author>
<published>2022-05-27T18:18:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=30975fb73d51f65d95e9508e4af9c85badd5388c'/>
<id>30975fb73d51f65d95e9508e4af9c85badd5388c</id>
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For Rockchip boards with the all rk8xx series PMICs (excluding the
rk808), it is sometimes desirable to not boot whenever the device is
plugged in. An example would be for the Odroid Go Advance.

This provides a configurable option to check the PMIC says it was
powered because of a plug-in event. If the value is 1 and this option
is selected, the device shuts down shortly after printing a message
to console stating the reason why it's shutting down. Powering up the
board with the power button is not affected.

This patch parallels the work done in the following patch series:
https://lore.kernel.org/u-boot/20220121133732.2397273-1-andre.przywara@arm.com/

Signed-off-by: Chris Morgan &lt;macromorgan@hotmail.com&gt;
Reviewed-by: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
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<pre>
For Rockchip boards with the all rk8xx series PMICs (excluding the
rk808), it is sometimes desirable to not boot whenever the device is
plugged in. An example would be for the Odroid Go Advance.

This provides a configurable option to check the PMIC says it was
powered because of a plug-in event. If the value is 1 and this option
is selected, the device shuts down shortly after printing a message
to console stating the reason why it's shutting down. Powering up the
board with the power button is not affected.

This patch parallels the work done in the following patch series:
https://lore.kernel.org/u-boot/20220121133732.2397273-1-andre.przywara@arm.com/

Signed-off-by: Chris Morgan &lt;macromorgan@hotmail.com&gt;
Reviewed-by: Jaehoon Chung &lt;jh80.chung@samsung.com&gt;
</pre>
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</content>
</entry>
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