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<title>u-boot.git/arch, branch v2024.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>mx6cuboxi: Convert to watchdog driver model</title>
<updated>2024-03-30T12:49:53+00:00</updated>
<author>
<name>Fabio Estevam</name>
<email>festevam@gmail.com</email>
</author>
<published>2024-03-27T14:18:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fc07cac02adebc87b69cd82f6ca6f0283d11cd5a'/>
<id>fc07cac02adebc87b69cd82f6ca6f0283d11cd5a</id>
<content type='text'>
Commit 68dcbdd594d4 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.

Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset.

Signed-off-by: Fabio Estevam &lt;festevam@gmail.com&gt;
Tested-by: Christian Gmeiner &lt;cgmeiner@igalia.com&gt;
</content>
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<pre>
Commit 68dcbdd594d4 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.

Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset.

Signed-off-by: Fabio Estevam &lt;festevam@gmail.com&gt;
Tested-by: Christian Gmeiner &lt;cgmeiner@igalia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>warp7: Convert to watchdog driver model</title>
<updated>2024-03-30T12:49:34+00:00</updated>
<author>
<name>Fabio Estevam</name>
<email>festevam@gmail.com</email>
</author>
<published>2024-03-27T13:46:51+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ea2b074a1ca646a9a88454753af0676599917b02'/>
<id>ea2b074a1ca646a9a88454753af0676599917b02</id>
<content type='text'>
Commit 68dcbdd594d4 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.

Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset.

Signed-off-by: Fabio Estevam &lt;festevam@gmail.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Commit 68dcbdd594d4 ("ARM: imx: Add weak default reset_cpu()") caused
the 'reset' command in U-Boot to not cause a board reset.

Fix it by switching to the watchdog driver model via sysreset, which
is the preferred method for implementing the watchdog reset.

Signed-off-by: Fabio Estevam &lt;festevam@gmail.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: dts: fix Ethernet on WeTek Hub/Play2</title>
<updated>2024-03-25T08:14:36+00:00</updated>
<author>
<name>Christian Hewitt</name>
<email>christianshewitt@gmail.com</email>
</author>
<published>2024-03-24T15:19:04+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cac77418d6be11445c3e1139f6763b5f5f5fe9fb'/>
<id>cac77418d6be11445c3e1139f6763b5f5f5fe9fb</id>
<content type='text'>
Placing the snps,reset content needed for Ethernet to probe in a common
uboot.dtsi results in the content not being used and broken Ethernet. Fix
this by creating two board specific dtsi files with the right content.

Fixes: 67d5128df950 ("ARM: dts: add support for WeTek Hub and WeTek Play2")
Signed-off-by: Christian Hewitt &lt;christianshewitt@gmail.com&gt;
Link: https://lore.kernel.org/r/20240324151905.3817732-2-christianshewitt@gmail.com
Signed-off-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Placing the snps,reset content needed for Ethernet to probe in a common
uboot.dtsi results in the content not being used and broken Ethernet. Fix
this by creating two board specific dtsi files with the right content.

Fixes: 67d5128df950 ("ARM: dts: add support for WeTek Hub and WeTek Play2")
Signed-off-by: Christian Hewitt &lt;christianshewitt@gmail.com&gt;
Link: https://lore.kernel.org/r/20240324151905.3817732-2-christianshewitt@gmail.com
Signed-off-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: dts: k3-am625-verdin-r5: Change CPU frequency to 800MHz</title>
<updated>2024-03-22T15:10:44+00:00</updated>
<author>
<name>Joao Paulo Goncalves</name>
<email>joao.goncalves@toradex.com</email>
</author>
<published>2024-03-19T14:04:27+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2bb18248c64e6a51b53c2571c0ca323a687c49c5'/>
<id>2bb18248c64e6a51b53c2571c0ca323a687c49c5</id>
<content type='text'>
The lowest speed grade of Toradex AM62 SoMs is K speed, resulting in a
max value of 800MHz for the CPU operating frequency. A solution with
runtime selection of the CPU frequency is already planned to avoid these
kinds of problems in the future.

Fixes: 8fb8a6d49977 ("arm: dts: k3-am625-verdin-r5:Change CPU frequency to 1000MHz")
Signed-off-by: Joao Paulo Goncalves &lt;joao.goncalves@toradex.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The lowest speed grade of Toradex AM62 SoMs is K speed, resulting in a
max value of 800MHz for the CPU operating frequency. A solution with
runtime selection of the CPU frequency is already planned to avoid these
kinds of problems in the future.

Fixes: 8fb8a6d49977 ("arm: dts: k3-am625-verdin-r5:Change CPU frequency to 1000MHz")
Signed-off-by: Joao Paulo Goncalves &lt;joao.goncalves@toradex.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: imx: imx8m: soc: Fix NPU/VPU fdt disable fixup</title>
<updated>2024-03-17T21:00:04+00:00</updated>
<author>
<name>Vitor Soares</name>
<email>vitor.soares@toradex.com</email>
</author>
<published>2024-03-15T14:44:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e648c4a3455a4d1880efe121602ed90a0bc9b53f'/>
<id>e648c4a3455a4d1880efe121602ed90a0bc9b53f</id>
<content type='text'>
On imx8m[m|p|q].dtsi, upstream Linux uses different names for NPU/VPU
IP block nodes. It leads variants without such HW block having it
enabled by default.

This patch adds the upstream Linux node's paths to the disable list while
keep the compatibility with downstream Linux.

Signed-off-by: Vitor Soares &lt;vitor.soares@toradex.com&gt;
Reviewed-by: Francesco Dolcini &lt;francesco.dolcini@toradex.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
On imx8m[m|p|q].dtsi, upstream Linux uses different names for NPU/VPU
IP block nodes. It leads variants without such HW block having it
enabled by default.

This patch adds the upstream Linux node's paths to the disable list while
keep the compatibility with downstream Linux.

Signed-off-by: Vitor Soares &lt;vitor.soares@toradex.com&gt;
Reviewed-by: Francesco Dolcini &lt;francesco.dolcini@toradex.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'mips-fixes-for-v2024.04' of https://source.denx.de/u-boot/custodians/u-boot-mips</title>
<updated>2024-03-13T21:15:46+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-03-13T21:15:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a81242099c56a0680658a3420f2a7ede08db2c14'/>
<id>a81242099c56a0680658a3420f2a7ede08db2c14</id>
<content type='text'>
- mips: implement __udivdi3 to fix building of SquashFS
- mips: fix bug in cache init on MIPS32r2 or later
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
- mips: implement __udivdi3 to fix building of SquashFS
- mips: fix bug in cache init on MIPS32r2 or later
</pre>
</div>
</content>
</entry>
<entry>
<title>mips: fix change_k0_cca()</title>
<updated>2024-03-13T20:15:40+00:00</updated>
<author>
<name>Daniel Schwierzeck</name>
<email>daniel.schwierzeck@gmail.com</email>
</author>
<published>2023-11-06T16:21:59+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6806a133cde6f99777925953ee046bf2f050d4ef'/>
<id>6806a133cde6f99777925953ee046bf2f050d4ef</id>
<content type='text'>
The intention of change_k0_cca() is to read the C0.Config register into
register $t0, update $t0 with the new cache coherency mode passed in $a0
and write back $t0 to C0.Config. With MIPS32 R2 or later instruction
sets, this can be achieved with a single instruction with INS. The
source and destination register of the INS instruction is passed as
first parameter. In case of change_k0_cca() it is register $t0. But
for writing back the updated value to C0.Config, the incorrect $a0
register is used. This is only correct in the MIPS32 R1 code path.

Fix the `mtc0` instruction to write back the value of the $t0 register.
Fix the MIPS32 R1 code path to also store the updated value in $t0.

Reported by user ddqxy138 on Github.
https://github.com/u-boot/u-boot/commit/b838586086af3278bcaead3720c7a18813cf4619

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The intention of change_k0_cca() is to read the C0.Config register into
register $t0, update $t0 with the new cache coherency mode passed in $a0
and write back $t0 to C0.Config. With MIPS32 R2 or later instruction
sets, this can be achieved with a single instruction with INS. The
source and destination register of the INS instruction is passed as
first parameter. In case of change_k0_cca() it is register $t0. But
for writing back the updated value to C0.Config, the incorrect $a0
register is used. This is only correct in the MIPS32 R1 code path.

Fix the `mtc0` instruction to write back the value of the $t0 register.
Fix the MIPS32 R1 code path to also store the updated value in $t0.

Reported by user ddqxy138 on Github.
https://github.com/u-boot/u-boot/commit/b838586086af3278bcaead3720c7a18813cf4619

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>mips: implement __udivdi3</title>
<updated>2024-03-13T20:15:40+00:00</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2023-09-18T06:11:39+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=811dd44b0b13cb1ea40392edfbe8ffa21c5b33ad'/>
<id>811dd44b0b13cb1ea40392edfbe8ffa21c5b33ad</id>
<content type='text'>
Squashfs wasn't compiling because the lldiv() directives
turn into __udivdi3 and we are using private libgcc.

After this squashfs compiles for MIPS.

Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Tested-by: Bartel Eerdekens &lt;barteleerdekens@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Squashfs wasn't compiling because the lldiv() directives
turn into __udivdi3 and we are using private libgcc.

After this squashfs compiles for MIPS.

Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Tested-by: Bartel Eerdekens &lt;barteleerdekens@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: dts: jh7110: Enable PLL node in SPL</title>
<updated>2024-03-12T06:36:13+00:00</updated>
<author>
<name>Bo Gan</name>
<email>ganboing@gmail.com</email>
</author>
<published>2024-03-06T03:00:11+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e6b7aeef3df206b9f2a47e715d643b735d18ae73'/>
<id>e6b7aeef3df206b9f2a47e715d643b735d18ae73</id>
<content type='text'>
Previously PLL node was missing from SPL dts. This caused BUS_ROOT
to stay on OSC clock (24Mhz). As a result, all peripherals have to
run at a much lower frequency, and loading from sdcard/emmc is slow.
Thus, enabling PLL node in dts to fix this.

Signed-off-by: Bo Gan &lt;ganboing@gmail.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Previously PLL node was missing from SPL dts. This caused BUS_ROOT
to stay on OSC clock (24Mhz). As a result, all peripherals have to
run at a much lower frequency, and loading from sdcard/emmc is slow.
Thus, enabling PLL node in dts to fix this.

Signed-off-by: Bo Gan &lt;ganboing@gmail.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>riscv: cpu: improve multi-letter extension detection in supports_extension()</title>
<updated>2024-03-12T06:36:13+00:00</updated>
<author>
<name>Conor Dooley</name>
<email>conor.dooley@microchip.com</email>
</author>
<published>2024-03-04T23:28:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0d95add3b1c7e17d979021505fcc138f74d95b88'/>
<id>0d95add3b1c7e17d979021505fcc138f74d95b88</id>
<content type='text'>
The first multi-letter extension after the single-letter extensions does
not have to be preceded by an underscore, which could cause the parser
to mistakenly find a single-letter extension after the start of the
multi-letter portion of the string.
Three letters precede multi-letter extensions (s, x &amp; z), none of which
are valid single-letter extensions. The dt-binding also allows
multi-letter extensions starting with h, but no such extension have been
frozen or ratified, and the unprivileged spec no longer uses "h" as a
prefix for multi-letter hypervisor extensions, having moved to "sh"
instead. For that reason, modify the parser to stop at s, x &amp; z to prevent
this overrun, ignoring h.

Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Reviewed-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The first multi-letter extension after the single-letter extensions does
not have to be preceded by an underscore, which could cause the parser
to mistakenly find a single-letter extension after the start of the
multi-letter portion of the string.
Three letters precede multi-letter extensions (s, x &amp; z), none of which
are valid single-letter extensions. The dt-binding also allows
multi-letter extensions starting with h, but no such extension have been
frozen or ratified, and the unprivileged spec no longer uses "h" as a
prefix for multi-letter hypervisor extensions, having moved to "sh"
instead. For that reason, modify the parser to stop at s, x &amp; z to prevent
this overrun, ignoring h.

Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Reviewed-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
</pre>
</div>
</content>
</entry>
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